A novel technique for run-time loading for MIPS soft-core processor

Soft-core processors on Field Programmable Gate Array (FPGA) chips are becoming an increasingly popular solution to support application-specific customization. However, any change in the assembly code of the implemented processor requires re-implement and download the soft-core on FPGA. This paper p...

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Hauptverfasser:	Bahaidarah, Mazen, Al-Obaisi, Hesham, Al-Sharif, Tariq, Al-Zahrani, Mosab, Awedh, Mohammad, Seddiq, Yasser
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Assembly CPU Digital Design Field programmable gate arrays FPGA GUI Loading MARS Microprocessors MIPS Python Random access memory Registers RISC Software tools UART Verilog
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