Improved architectures for the add-compare-select operation in long constraint length Viterbi decoding
While turbo coding techniques have received much recent attention for their extraordinary coding gains, these techniques inherently suffer latency limitations unacceptable in most telephony applications. Long constraint length (LCL) Viterbi decoding (VD) techniques hold promise for significant codin...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1998-01, Vol.33 (1), p.151-155 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 33 |
| creator | Page, K. Chau, P.M. |
| description | While turbo coding techniques have received much recent attention for their extraordinary coding gains, these techniques inherently suffer latency limitations unacceptable in most telephony applications. Long constraint length (LCL) Viterbi decoding (VD) techniques hold promise for significant coding gains at low latencies. This paper presents two novel architectures for the add-compare-select unit of an LCL VD. The derived bit-serial circuits are shown to be more efficient than traditional bit-serial methods with one solution 24% more efficient than traditional approaches and requiring only 1/2 the I/O. Using these techniques, a hardware Viterbi decoder was designed, built, and tested. |
| doi_str_mv | 10.1109/4.654948 |
| format | Article |
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Long constraint length (LCL) Viterbi decoding (VD) techniques hold promise for significant coding gains at low latencies. This paper presents two novel architectures for the add-compare-select unit of an LCL VD. The derived bit-serial circuits are shown to be more efficient than traditional bit-serial methods with one solution 24% more efficient than traditional approaches and requiring only 1/2 the I/O. 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| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_ieee_primary_654948 |
| source | IEEE/IET Electronic Library (IEL) |
| subjects | Circuit testing Delay Digital communication Forward error correction Hardware Maximum likelihood decoding Registers Telephony Turbo codes Viterbi algorithm |
| title | Improved architectures for the add-compare-select operation in long constraint length Viterbi decoding |
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