Improved architectures for the add-compare-select operation in long constraint length Viterbi decoding

While turbo coding techniques have received much recent attention for their extraordinary coding gains, these techniques inherently suffer latency limitations unacceptable in most telephony applications. Long constraint length (LCL) Viterbi decoding (VD) techniques hold promise for significant coding gains at low latencies. This paper presents two novel architectures for the add-compare-select unit of an LCL VD. The derived bit-serial circuits are shown to be more efficient than traditional bit-serial methods with one solution 24% more efficient than traditional approaches and requiring only 1/2 the I/O. Using these techniques, a hardware Viterbi decoder was designed, built, and tested.