Bit Cost Scalable (BiCS) technology for future ultra high density memories
We proposed Bit Cost Scalable (BiCS) technology in 2007 as a three-dimensional memory for the future ultra high density storage devices, which extremely reduce the bit costs by vertically stacking memory arrays with punch and plug process. We've applied it to just NAND flash, which is BiCS Flas...
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creator | Nitayama, A. Aochi, H. |
description | We proposed Bit Cost Scalable (BiCS) technology in 2007 as a three-dimensional memory for the future ultra high density storage devices, which extremely reduce the bit costs by vertically stacking memory arrays with punch and plug process. We've applied it to just NAND flash, which is BiCS Flash memory, and established the mass production technology. Moreover, we can apply the BiCS technology to various memories. The critical issues and the comparison among various 3D NAND Flash-type memories are to be discussed, as well. |
doi_str_mv | 10.1109/VLSI-TSA.2013.6545626 |
format | Conference Proceeding |
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We've applied it to just NAND flash, which is BiCS Flash memory, and established the mass production technology. Moreover, we can apply the BiCS technology to various memories. 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We've applied it to just NAND flash, which is BiCS Flash memory, and established the mass production technology. Moreover, we can apply the BiCS technology to various memories. The critical issues and the comparison among various 3D NAND Flash-type memories are to be discussed, as well.</description><subject>Electrodes</subject><subject>Flash memories</subject><subject>Logic gates</subject><subject>SONOS devices</subject><subject>Three-dimensional displays</subject><subject>Very large scale integration</subject><isbn>1467330817</isbn><isbn>9781467330817</isbn><isbn>1467364223</isbn><isbn>9781467364225</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj81KxDAURiMiqOM8gQhZ6qL1Jre5aZczZdSRgouObof-JNNIO5U2XfTtFezq4yzOgY-xBwGhEJA8f2X5Pjjkm1CCwJBUpEjSBbsVEWmkSEq8XAAhFvqarcfxGwD-ZA1JdMPet87ztB89z6uiLcrW8MetS_Mn7k3VnPu2P83c9gO3k58Gw6fWDwVv3KnhtTmPzs-8M10_ODPesStbtKNZL7tiny-7Q_oWZB-v-3STBU5GwgcRkFJQSNSlToCsNYlVUJdEqAhjHSOJpKylrgWUlZBVnFhLqAnLOlYIuGL3_11njDn-DK4rhvm4fMdf0KZMqA</recordid><startdate>201304</startdate><enddate>201304</enddate><creator>Nitayama, A.</creator><creator>Aochi, H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201304</creationdate><title>Bit Cost Scalable (BiCS) technology for future ultra high density memories</title><author>Nitayama, A. ; Aochi, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i241t-406550a237b7906ffe9f50db6635638783619bd27d10bc12c89ff63763bd85303</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Electrodes</topic><topic>Flash memories</topic><topic>Logic gates</topic><topic>SONOS devices</topic><topic>Three-dimensional displays</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Nitayama, A.</creatorcontrib><creatorcontrib>Aochi, H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nitayama, A.</au><au>Aochi, H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Bit Cost Scalable (BiCS) technology for future ultra high density memories</atitle><btitle>2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)</btitle><stitle>VLSI-TSA</stitle><date>2013-04</date><risdate>2013</risdate><spage>1</spage><epage>2</epage><pages>1-2</pages><isbn>1467330817</isbn><isbn>9781467330817</isbn><eisbn>1467364223</eisbn><eisbn>9781467364225</eisbn><abstract>We proposed Bit Cost Scalable (BiCS) technology in 2007 as a three-dimensional memory for the future ultra high density storage devices, which extremely reduce the bit costs by vertically stacking memory arrays with punch and plug process. We've applied it to just NAND flash, which is BiCS Flash memory, and established the mass production technology. Moreover, we can apply the BiCS technology to various memories. The critical issues and the comparison among various 3D NAND Flash-type memories are to be discussed, as well.</abstract><pub>IEEE</pub><doi>10.1109/VLSI-TSA.2013.6545626</doi><tpages>2</tpages></addata></record> |
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subjects | Electrodes Flash memories Logic gates SONOS devices Three-dimensional displays Very large scale integration |
title | Bit Cost Scalable (BiCS) technology for future ultra high density memories |
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