A low-power design methodology for sigma-delta modulators with relaxation of required circuit specifications

A design methodology of high-order sigma-delta modulators (SDMs) with relaxation of required circuit specifications is proposed to reduce the required power consumption and to be suitable for the nano-scale circuit. According to the proposed design flow, more relaxed circuit specifications can be se...

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Hauptverfasser:	Jia-Hua Hong, Ming-Chun Liang, Jing-Yi Wong, Shuenn-Yuh Lee
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Bandwidth Design methodology Gain GSM Modulation Sigma-delta modulation System performance
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creator	Jia-Hua Hong Ming-Chun Liang Jing-Yi Wong Shuenn-Yuh Lee
description	A design methodology of high-order sigma-delta modulators (SDMs) with relaxation of required circuit specifications is proposed to reduce the required power consumption and to be suitable for the nano-scale circuit. According to the proposed design flow, more relaxed circuit specifications can be selected so that designers can maintain system performance. One design example is employed to verify the proposed design flow. Circuit-level simulation reveals that the power consumption is lower under the same system performance compared with a conventional design flow. The circuits are implement with TSMC 90nm 1P9M CMOS process and the measured signal-to-noise distortion ratio (SNDR) is 64.5 dB, with a power consumption of 303μW.
doi_str_mv	10.1109/VLDI-DAT.2013.6533872
format	Conference Proceeding
fullrecord	<record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6533872</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6533872</ieee_id><sourcerecordid>6533872</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-955d7ff6a0a0fd27ffea466024123bc7cb90d50f17966fe9937164932bea82333</originalsourceid><addsrcrecordid>eNo1UEtPAjEYrDEmKvILjEn_wGJf226PBHyQkHhBr6S7_Qo1XYptCfLv3Sie5pGZOQxCD5RMKCX68WM5X1Tz6WrCCOUTWXPeKHaBxlo1VEjFheBSXKLbf1GLazTO-ZMQMvQV0fQGhSkO8Vjt4xEStpD9Zod7KNtoY4ibE3Yx4cHsTWUhFIP7aA_BlJgyPvqyxQmC-TbFxx2OblBfB5_A4s6n7uALznvovPPdbyLfoStnQobxGUfo_flpNXutlm8vi9l0WXmq6lLpurbKOWmIIc6ygYIRUhImKONtp7pWE1sTR5WW0oHWXFEpNGctmIZxzkfo_m_XA8B6n3xv0ml9Poj_AEcOXI0</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A low-power design methodology for sigma-delta modulators with relaxation of required circuit specifications</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Jia-Hua Hong ; Ming-Chun Liang ; Jing-Yi Wong ; Shuenn-Yuh Lee</creator><creatorcontrib>Jia-Hua Hong ; Ming-Chun Liang ; Jing-Yi Wong ; Shuenn-Yuh Lee</creatorcontrib><description>A design methodology of high-order sigma-delta modulators (SDMs) with relaxation of required circuit specifications is proposed to reduce the required power consumption and to be suitable for the nano-scale circuit. According to the proposed design flow, more relaxed circuit specifications can be selected so that designers can maintain system performance. One design example is employed to verify the proposed design flow. Circuit-level simulation reveals that the power consumption is lower under the same system performance compared with a conventional design flow. The circuits are implement with TSMC 90nm 1P9M CMOS process and the measured signal-to-noise distortion ratio (SNDR) is 64.5 dB, with a power consumption of 303μW.</description><identifier>ISBN: 1467344354</identifier><identifier>ISBN: 9781467344357</identifier><identifier>EISBN: 9781467344364</identifier><identifier>EISBN: 1467344362</identifier><identifier>DOI: 10.1109/VLDI-DAT.2013.6533872</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bandwidth ; Design methodology ; Gain ; GSM ; Modulation ; Sigma-delta modulation ; System performance</subject><ispartof>2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT), 2013, p.1-4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6533872$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6533872$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jia-Hua Hong</creatorcontrib><creatorcontrib>Ming-Chun Liang</creatorcontrib><creatorcontrib>Jing-Yi Wong</creatorcontrib><creatorcontrib>Shuenn-Yuh Lee</creatorcontrib><title>A low-power design methodology for sigma-delta modulators with relaxation of required circuit specifications</title><title>2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)</title><addtitle>VLDI-DAT</addtitle><description>A design methodology of high-order sigma-delta modulators (SDMs) with relaxation of required circuit specifications is proposed to reduce the required power consumption and to be suitable for the nano-scale circuit. According to the proposed design flow, more relaxed circuit specifications can be selected so that designers can maintain system performance. One design example is employed to verify the proposed design flow. Circuit-level simulation reveals that the power consumption is lower under the same system performance compared with a conventional design flow. The circuits are implement with TSMC 90nm 1P9M CMOS process and the measured signal-to-noise distortion ratio (SNDR) is 64.5 dB, with a power consumption of 303μW.</description><subject>Bandwidth</subject><subject>Design methodology</subject><subject>Gain</subject><subject>GSM</subject><subject>Modulation</subject><subject>Sigma-delta modulation</subject><subject>System performance</subject><isbn>1467344354</isbn><isbn>9781467344357</isbn><isbn>9781467344364</isbn><isbn>1467344362</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1UEtPAjEYrDEmKvILjEn_wGJf226PBHyQkHhBr6S7_Qo1XYptCfLv3Sie5pGZOQxCD5RMKCX68WM5X1Tz6WrCCOUTWXPeKHaBxlo1VEjFheBSXKLbf1GLazTO-ZMQMvQV0fQGhSkO8Vjt4xEStpD9Zod7KNtoY4ibE3Yx4cHsTWUhFIP7aA_BlJgyPvqyxQmC-TbFxx2OblBfB5_A4s6n7uALznvovPPdbyLfoStnQobxGUfo_flpNXutlm8vi9l0WXmq6lLpurbKOWmIIc6ygYIRUhImKONtp7pWE1sTR5WW0oHWXFEpNGctmIZxzkfo_m_XA8B6n3xv0ml9Poj_AEcOXI0</recordid><startdate>201304</startdate><enddate>201304</enddate><creator>Jia-Hua Hong</creator><creator>Ming-Chun Liang</creator><creator>Jing-Yi Wong</creator><creator>Shuenn-Yuh Lee</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201304</creationdate><title>A low-power design methodology for sigma-delta modulators with relaxation of required circuit specifications</title><author>Jia-Hua Hong ; Ming-Chun Liang ; Jing-Yi Wong ; Shuenn-Yuh Lee</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-955d7ff6a0a0fd27ffea466024123bc7cb90d50f17966fe9937164932bea82333</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Bandwidth</topic><topic>Design methodology</topic><topic>Gain</topic><topic>GSM</topic><topic>Modulation</topic><topic>Sigma-delta modulation</topic><topic>System performance</topic><toplevel>online_resources</toplevel><creatorcontrib>Jia-Hua Hong</creatorcontrib><creatorcontrib>Ming-Chun Liang</creatorcontrib><creatorcontrib>Jing-Yi Wong</creatorcontrib><creatorcontrib>Shuenn-Yuh Lee</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jia-Hua Hong</au><au>Ming-Chun Liang</au><au>Jing-Yi Wong</au><au>Shuenn-Yuh Lee</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A low-power design methodology for sigma-delta modulators with relaxation of required circuit specifications</atitle><btitle>2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)</btitle><stitle>VLDI-DAT</stitle><date>2013-04</date><risdate>2013</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><isbn>1467344354</isbn><isbn>9781467344357</isbn><eisbn>9781467344364</eisbn><eisbn>1467344362</eisbn><abstract>A design methodology of high-order sigma-delta modulators (SDMs) with relaxation of required circuit specifications is proposed to reduce the required power consumption and to be suitable for the nano-scale circuit. According to the proposed design flow, more relaxed circuit specifications can be selected so that designers can maintain system performance. One design example is employed to verify the proposed design flow. Circuit-level simulation reveals that the power consumption is lower under the same system performance compared with a conventional design flow. The circuits are implement with TSMC 90nm 1P9M CMOS process and the measured signal-to-noise distortion ratio (SNDR) is 64.5 dB, with a power consumption of 303μW.</abstract><pub>IEEE</pub><doi>10.1109/VLDI-DAT.2013.6533872</doi><tpages>4</tpages></addata></record>
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identifier	ISBN: 1467344354
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subjects	Bandwidth Design methodology Gain GSM Modulation Sigma-delta modulation System performance
title	A low-power design methodology for sigma-delta modulators with relaxation of required circuit specifications
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-31T12%3A48%3A30IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20low-power%20design%20methodology%20for%20sigma-delta%20modulators%20with%20relaxation%20of%20required%20circuit%20specifications&rft.btitle=2013%20International%20Symposium%20onVLSI%20Design,%20Automation,%20and%20Test%20(VLSI-DAT)&rft.au=Jia-Hua%20Hong&rft.date=2013-04&rft.spage=1&rft.epage=4&rft.pages=1-4&rft.isbn=1467344354&rft.isbn_list=9781467344357&rft_id=info:doi/10.1109/VLDI-DAT.2013.6533872&rft_dat=%3Cieee_6IE%3E6533872%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781467344364&rft.eisbn_list=1467344362&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6533872&rfr_iscdi=true