A novel processor design flow using processor description language applied to a vector coprocessor
We have developed a vector coprocessor for a wireless baseband SoC for mobile devices using processor description language. The design of the vector coprocessor is highly-complex and it requires a lot of design time and costs with a conventional design flow. To address this problem, we developed an...
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| creator | Ito, Makiko Tomono, M. Yi Ge Takebe, Y. Toichi, M. Mouri, M. Hirose, Y. |
| description | We have developed a vector coprocessor for a wireless baseband SoC for mobile devices using processor description language. The design of the vector coprocessor is highly-complex and it requires a lot of design time and costs with a conventional design flow. To address this problem, we developed an architecture design flow with an untimed model and a performance estimator. We achieved 4.5 times better design efficiency compared to a conventional implementation design flow with a timed model. As a result, we were able to reduce design and optimization time dramatically. |
| doi_str_mv | 10.1109/VLDI-DAT.2013.6533844 |
| format | Conference Proceeding |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Computer architecture Coprocessors Optimization Pipelines Registers Vectors Wireless communication |
| title | A novel processor design flow using processor description language applied to a vector coprocessor |
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