FPGA implementation of high speed 8-bit Vedic multiplier using barrel shifter

This paper describes the implementation of an 8-bit Vedic multiplier enhanced in terms of propagation delay when compared with conventional multiplier like array multiplier, Braun multiplier, modified booth multiplier and Wallace tree multiplier. In our design we have utilized 8-bit barrel shifter w...

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Bibliographische Detailangaben

Hauptverfasser:	Kumar, U. C. S. P., Goud, A. S., Radhika, A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Adders Barrel shifter base selection module Clocks Computer architecture Delays Field programmable gate arrays Indexes power index determinant Propagation delay
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