Program/erase speed, endurance, retention, and disturbance characteristics of single-poly embedded flash cells
N-channel and P-channel single-poly embedded flash (eflash) memory cells were implemented in a standard CMOS logic process. Among the different configurations based on standard I/O devices, the N-channel cell with a PMOS-PMOS-NMOS combo and the P-channel cell with an NMOS-NMOS-PMOS combo were found...
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| creator | Seung-Hwan Song Jongyeon Kim Kim, C. H. |
| description | N-channel and P-channel single-poly embedded flash (eflash) memory cells were implemented in a standard CMOS logic process. Among the different configurations based on standard I/O devices, the N-channel cell with a PMOS-PMOS-NMOS combo and the P-channel cell with an NMOS-NMOS-PMOS combo were found to be most attractive in terms of program/erase performance, while the cell with a coupling device having P+ poly showed longer retention characteristic than the cells with a coupling device having N+ poly. Negligible program disturbance and floating gate coupling were observed in all cell types. |
| doi_str_mv | 10.1109/IRPS.2013.6532095 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6532095</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6532095</ieee_id><sourcerecordid>6532095</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-9888ada859df32232dd90772113ccd65ccdb247fb14565ab28ecde4ff5f3ec433</originalsourceid><addsrcrecordid>eNpVkMtqwzAURNUXNE3zAaUbfUCc6EqWJS1L6SMQaOhjHWTpKlFx7CA5i_x9XZpNZzEDc2AWQ8gdsBkAM_PF--pjxhmIWSUFZ0aekYlRGkplDINB52QERugCtIGLf4zry4HJEgrFeHVNbnL-ZowzoasRaVep2yS7m2OyGWneI_opxdYfkm0dTmnCHts-du2U2tZTH3N_SPUvo25rk3U9pqGLLtMu0BzbTYPFvmuOFHc1eo-ehsbmLXXYNPmWXAXbZJyccky-np8-H1-L5dvL4vFhWURQsi-M1tp6q6XxQXAuuPeGKcUBhHO-koPVvFShhlJW0tZco_NYhiCDQFcKMSb3f7sREdf7FHc2Hden68QPY4JgEw</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Program/erase speed, endurance, retention, and disturbance characteristics of single-poly embedded flash cells</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Seung-Hwan Song ; Jongyeon Kim ; Kim, C. H.</creator><creatorcontrib>Seung-Hwan Song ; Jongyeon Kim ; Kim, C. H.</creatorcontrib><description>N-channel and P-channel single-poly embedded flash (eflash) memory cells were implemented in a standard CMOS logic process. Among the different configurations based on standard I/O devices, the N-channel cell with a PMOS-PMOS-NMOS combo and the P-channel cell with an NMOS-NMOS-PMOS combo were found to be most attractive in terms of program/erase performance, while the cell with a coupling device having P+ poly showed longer retention characteristic than the cells with a coupling device having N+ poly. Negligible program disturbance and floating gate coupling were observed in all cell types.</description><identifier>ISSN: 1541-7026</identifier><identifier>ISBN: 9781479901128</identifier><identifier>ISBN: 1479901121</identifier><identifier>EISSN: 1938-1891</identifier><identifier>EISBN: 9781479901111</identifier><identifier>EISBN: 147990113X</identifier><identifier>EISBN: 1479901113</identifier><identifier>EISBN: 9781479901135</identifier><identifier>DOI: 10.1109/IRPS.2013.6532095</identifier><language>eng</language><publisher>IEEE</publisher><subject>Couplings ; Current measurement ; Embedded Flash ; Flash Program/Erase ; Flash Reliability ; Logic gates ; Nonvolatile memory ; Single-Poly Embedded Flash Cell ; Temperature measurement ; Transistors</subject><ispartof>2013 IEEE International Reliability Physics Symposium (IRPS), 2013, p.MY.4.1-MY.4.6</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6532095$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6532095$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Seung-Hwan Song</creatorcontrib><creatorcontrib>Jongyeon Kim</creatorcontrib><creatorcontrib>Kim, C. H.</creatorcontrib><title>Program/erase speed, endurance, retention, and disturbance characteristics of single-poly embedded flash cells</title><title>2013 IEEE International Reliability Physics Symposium (IRPS)</title><addtitle>IRPS</addtitle><description>N-channel and P-channel single-poly embedded flash (eflash) memory cells were implemented in a standard CMOS logic process. Among the different configurations based on standard I/O devices, the N-channel cell with a PMOS-PMOS-NMOS combo and the P-channel cell with an NMOS-NMOS-PMOS combo were found to be most attractive in terms of program/erase performance, while the cell with a coupling device having P+ poly showed longer retention characteristic than the cells with a coupling device having N+ poly. Negligible program disturbance and floating gate coupling were observed in all cell types.</description><subject>Couplings</subject><subject>Current measurement</subject><subject>Embedded Flash</subject><subject>Flash Program/Erase</subject><subject>Flash Reliability</subject><subject>Logic gates</subject><subject>Nonvolatile memory</subject><subject>Single-Poly Embedded Flash Cell</subject><subject>Temperature measurement</subject><subject>Transistors</subject><issn>1541-7026</issn><issn>1938-1891</issn><isbn>9781479901128</isbn><isbn>1479901121</isbn><isbn>9781479901111</isbn><isbn>147990113X</isbn><isbn>1479901113</isbn><isbn>9781479901135</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkMtqwzAURNUXNE3zAaUbfUCc6EqWJS1L6SMQaOhjHWTpKlFx7CA5i_x9XZpNZzEDc2AWQ8gdsBkAM_PF--pjxhmIWSUFZ0aekYlRGkplDINB52QERugCtIGLf4zry4HJEgrFeHVNbnL-ZowzoasRaVep2yS7m2OyGWneI_opxdYfkm0dTmnCHts-du2U2tZTH3N_SPUvo25rk3U9pqGLLtMu0BzbTYPFvmuOFHc1eo-ehsbmLXXYNPmWXAXbZJyccky-np8-H1-L5dvL4vFhWURQsi-M1tp6q6XxQXAuuPeGKcUBhHO-koPVvFShhlJW0tZco_NYhiCDQFcKMSb3f7sREdf7FHc2Hden68QPY4JgEw</recordid><startdate>201304</startdate><enddate>201304</enddate><creator>Seung-Hwan Song</creator><creator>Jongyeon Kim</creator><creator>Kim, C. H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201304</creationdate><title>Program/erase speed, endurance, retention, and disturbance characteristics of single-poly embedded flash cells</title><author>Seung-Hwan Song ; Jongyeon Kim ; Kim, C. H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-9888ada859df32232dd90772113ccd65ccdb247fb14565ab28ecde4ff5f3ec433</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Couplings</topic><topic>Current measurement</topic><topic>Embedded Flash</topic><topic>Flash Program/Erase</topic><topic>Flash Reliability</topic><topic>Logic gates</topic><topic>Nonvolatile memory</topic><topic>Single-Poly Embedded Flash Cell</topic><topic>Temperature measurement</topic><topic>Transistors</topic><toplevel>online_resources</toplevel><creatorcontrib>Seung-Hwan Song</creatorcontrib><creatorcontrib>Jongyeon Kim</creatorcontrib><creatorcontrib>Kim, C. H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Seung-Hwan Song</au><au>Jongyeon Kim</au><au>Kim, C. H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Program/erase speed, endurance, retention, and disturbance characteristics of single-poly embedded flash cells</atitle><btitle>2013 IEEE International Reliability Physics Symposium (IRPS)</btitle><stitle>IRPS</stitle><date>2013-04</date><risdate>2013</risdate><spage>MY.4.1</spage><epage>MY.4.6</epage><pages>MY.4.1-MY.4.6</pages><issn>1541-7026</issn><eissn>1938-1891</eissn><isbn>9781479901128</isbn><isbn>1479901121</isbn><eisbn>9781479901111</eisbn><eisbn>147990113X</eisbn><eisbn>1479901113</eisbn><eisbn>9781479901135</eisbn><abstract>N-channel and P-channel single-poly embedded flash (eflash) memory cells were implemented in a standard CMOS logic process. Among the different configurations based on standard I/O devices, the N-channel cell with a PMOS-PMOS-NMOS combo and the P-channel cell with an NMOS-NMOS-PMOS combo were found to be most attractive in terms of program/erase performance, while the cell with a coupling device having P+ poly showed longer retention characteristic than the cells with a coupling device having N+ poly. Negligible program disturbance and floating gate coupling were observed in all cell types.</abstract><pub>IEEE</pub><doi>10.1109/IRPS.2013.6532095</doi></addata></record> |
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| identifier | ISSN: 1541-7026 |
| ispartof | 2013 IEEE International Reliability Physics Symposium (IRPS), 2013, p.MY.4.1-MY.4.6 |
| issn | 1541-7026 1938-1891 |
| language | eng |
| recordid | cdi_ieee_primary_6532095 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Couplings Current measurement Embedded Flash Flash Program/Erase Flash Reliability Logic gates Nonvolatile memory Single-Poly Embedded Flash Cell Temperature measurement Transistors |
| title | Program/erase speed, endurance, retention, and disturbance characteristics of single-poly embedded flash cells |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-20T20%3A43%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Program/erase%20speed,%20endurance,%20retention,%20and%20disturbance%20characteristics%20of%20single-poly%20embedded%20flash%20cells&rft.btitle=2013%20IEEE%20International%20Reliability%20Physics%20Symposium%20(IRPS)&rft.au=Seung-Hwan%20Song&rft.date=2013-04&rft.spage=MY.4.1&rft.epage=MY.4.6&rft.pages=MY.4.1-MY.4.6&rft.issn=1541-7026&rft.eissn=1938-1891&rft.isbn=9781479901128&rft.isbn_list=1479901121&rft_id=info:doi/10.1109/IRPS.2013.6532095&rft_dat=%3Cieee_6IE%3E6532095%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781479901111&rft.eisbn_list=147990113X&rft.eisbn_list=1479901113&rft.eisbn_list=9781479901135&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6532095&rfr_iscdi=true |