New Erase Constraint for the Junction-Less Charge-Trap Memory Array in Cylindrical Geometry

This paper presents a detailed simulation analysis of the erase performance of junction-less charge-trap memory arrays in the cylindrical geometry, showing that a saturation of the erased threshold voltage occurs as a result of incomplete inversion of the intercell regions when positive charge is st...

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Veröffentlicht in:	IEEE transactions on electron devices 2013-07, Vol.60 (7), p.2203-2208
Hauptverfasser:	Maconi, A., Compagnoni, C. M., Spinelli, A. S., Lacaita, A. L.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Arrays Charge-trap memories Design. Technologies. Operation analysis. Testing Dielectrics Doping Electronics Electrostatics erase saturation Exact sciences and technology flash memories Geometry Integrated circuits Integrated circuits by function (including memories and processors) Logic gates semiconductor device modeling Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Substrates
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