New Erase Constraint for the Junction-Less Charge-Trap Memory Array in Cylindrical Geometry
This paper presents a detailed simulation analysis of the erase performance of junction-less charge-trap memory arrays in the cylindrical geometry, showing that a saturation of the erased threshold voltage occurs as a result of incomplete inversion of the intercell regions when positive charge is st...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on electron devices 2013-07, Vol.60 (7), p.2203-2208 |
|---|---|
| Hauptverfasser: | , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 2208 |
|---|---|
| container_issue | 7 |
| container_start_page | 2203 |
| container_title | IEEE transactions on electron devices |
| container_volume | 60 |
| creator | Maconi, A. Compagnoni, C. M. Spinelli, A. S. Lacaita, A. L. |
| description | This paper presents a detailed simulation analysis of the erase performance of junction-less charge-trap memory arrays in the cylindrical geometry, showing that a saturation of the erased threshold voltage occurs as a result of incomplete inversion of the intercell regions when positive charge is stored in the cells. This erase saturation issue is investigated as a function of string and cell parameters, revealing lower erase capabilities for large cell-to-cell separation, small substrate radius, and small equivalent-oxide thickness of the gate stack. These results add new constraints to the design of cylindrical junction-less memory technologies. |
| doi_str_mv | 10.1109/TED.2013.2264324 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_6527952</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6527952</ieee_id><sourcerecordid>3003612451</sourcerecordid><originalsourceid>FETCH-LOGICAL-c321t-c148701f6ccd7b49fc3b9483af8fec49b5ada6419dc260bfce285ecf2aac55873</originalsourceid><addsrcrecordid>eNo9kM1Lw0AQxRdRsFbvgpcF8Zi6n9nNscRalaqXevIQNttZm9ImdTZF8t-b0tLTMMx7b3g_Qm45G3HOssf55GkkGJcjIVIlhTojA661SbJUpedkwBi3SSatvCRXMa76NVVKDMj3B_zRCboING_q2KKr6paGBmm7BPq2q31bNXUygxhpvnT4A8kc3Za-w6bBjo4RXUermubduqoXWHm3plNoNtBid00ugltHuDnOIfl6nszzl2T2OX3Nx7PES8HbxHNlDeMh9X5hSpUFL8tMWemCDeBVVmq3cKni2cKLlJXBg7AafBDOea2tkUNyf8jdYvO7g9gWq2aHdf-y4NIwKwzriw8JO6g8NjEihGKL1cZhV3BW7BEWPcJij7A4IuwtD8dgF_tiAV3tq3jyCaOs0pr1uruDrgKA0znVwmRayH_ccHoT</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1370827038</pqid></control><display><type>article</type><title>New Erase Constraint for the Junction-Less Charge-Trap Memory Array in Cylindrical Geometry</title><source>IEEE Xplore</source><creator>Maconi, A. ; Compagnoni, C. M. ; Spinelli, A. S. ; Lacaita, A. L.</creator><creatorcontrib>Maconi, A. ; Compagnoni, C. M. ; Spinelli, A. S. ; Lacaita, A. L.</creatorcontrib><description>This paper presents a detailed simulation analysis of the erase performance of junction-less charge-trap memory arrays in the cylindrical geometry, showing that a saturation of the erased threshold voltage occurs as a result of incomplete inversion of the intercell regions when positive charge is stored in the cells. This erase saturation issue is investigated as a function of string and cell parameters, revealing lower erase capabilities for large cell-to-cell separation, small substrate radius, and small equivalent-oxide thickness of the gate stack. These results add new constraints to the design of cylindrical junction-less memory technologies.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2013.2264324</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Arrays ; Charge-trap memories ; Design. Technologies. Operation analysis. Testing ; Dielectrics ; Doping ; Electronics ; Electrostatics ; erase saturation ; Exact sciences and technology ; flash memories ; Geometry ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Logic gates ; semiconductor device modeling ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Substrates</subject><ispartof>IEEE transactions on electron devices, 2013-07, Vol.60 (7), p.2203-2208</ispartof><rights>2014 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Jul 2013</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c321t-c148701f6ccd7b49fc3b9483af8fec49b5ada6419dc260bfce285ecf2aac55873</citedby><cites>FETCH-LOGICAL-c321t-c148701f6ccd7b49fc3b9483af8fec49b5ada6419dc260bfce285ecf2aac55873</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6527952$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6527952$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=27484550$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Maconi, A.</creatorcontrib><creatorcontrib>Compagnoni, C. M.</creatorcontrib><creatorcontrib>Spinelli, A. S.</creatorcontrib><creatorcontrib>Lacaita, A. L.</creatorcontrib><title>New Erase Constraint for the Junction-Less Charge-Trap Memory Array in Cylindrical Geometry</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>This paper presents a detailed simulation analysis of the erase performance of junction-less charge-trap memory arrays in the cylindrical geometry, showing that a saturation of the erased threshold voltage occurs as a result of incomplete inversion of the intercell regions when positive charge is stored in the cells. This erase saturation issue is investigated as a function of string and cell parameters, revealing lower erase capabilities for large cell-to-cell separation, small substrate radius, and small equivalent-oxide thickness of the gate stack. These results add new constraints to the design of cylindrical junction-less memory technologies.</description><subject>Applied sciences</subject><subject>Arrays</subject><subject>Charge-trap memories</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Dielectrics</subject><subject>Doping</subject><subject>Electronics</subject><subject>Electrostatics</subject><subject>erase saturation</subject><subject>Exact sciences and technology</subject><subject>flash memories</subject><subject>Geometry</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Logic gates</subject><subject>semiconductor device modeling</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Substrates</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM1Lw0AQxRdRsFbvgpcF8Zi6n9nNscRalaqXevIQNttZm9ImdTZF8t-b0tLTMMx7b3g_Qm45G3HOssf55GkkGJcjIVIlhTojA661SbJUpedkwBi3SSatvCRXMa76NVVKDMj3B_zRCboING_q2KKr6paGBmm7BPq2q31bNXUygxhpvnT4A8kc3Za-w6bBjo4RXUermubduqoXWHm3plNoNtBid00ugltHuDnOIfl6nszzl2T2OX3Nx7PES8HbxHNlDeMh9X5hSpUFL8tMWemCDeBVVmq3cKni2cKLlJXBg7AafBDOea2tkUNyf8jdYvO7g9gWq2aHdf-y4NIwKwzriw8JO6g8NjEihGKL1cZhV3BW7BEWPcJij7A4IuwtD8dgF_tiAV3tq3jyCaOs0pr1uruDrgKA0znVwmRayH_ccHoT</recordid><startdate>20130701</startdate><enddate>20130701</enddate><creator>Maconi, A.</creator><creator>Compagnoni, C. M.</creator><creator>Spinelli, A. S.</creator><creator>Lacaita, A. L.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>20130701</creationdate><title>New Erase Constraint for the Junction-Less Charge-Trap Memory Array in Cylindrical Geometry</title><author>Maconi, A. ; Compagnoni, C. M. ; Spinelli, A. S. ; Lacaita, A. L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c321t-c148701f6ccd7b49fc3b9483af8fec49b5ada6419dc260bfce285ecf2aac55873</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Applied sciences</topic><topic>Arrays</topic><topic>Charge-trap memories</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Dielectrics</topic><topic>Doping</topic><topic>Electronics</topic><topic>Electrostatics</topic><topic>erase saturation</topic><topic>Exact sciences and technology</topic><topic>flash memories</topic><topic>Geometry</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Logic gates</topic><topic>semiconductor device modeling</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Substrates</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Maconi, A.</creatorcontrib><creatorcontrib>Compagnoni, C. M.</creatorcontrib><creatorcontrib>Spinelli, A. S.</creatorcontrib><creatorcontrib>Lacaita, A. L.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Maconi, A.</au><au>Compagnoni, C. M.</au><au>Spinelli, A. S.</au><au>Lacaita, A. L.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>New Erase Constraint for the Junction-Less Charge-Trap Memory Array in Cylindrical Geometry</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2013-07-01</date><risdate>2013</risdate><volume>60</volume><issue>7</issue><spage>2203</spage><epage>2208</epage><pages>2203-2208</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>This paper presents a detailed simulation analysis of the erase performance of junction-less charge-trap memory arrays in the cylindrical geometry, showing that a saturation of the erased threshold voltage occurs as a result of incomplete inversion of the intercell regions when positive charge is stored in the cells. This erase saturation issue is investigated as a function of string and cell parameters, revealing lower erase capabilities for large cell-to-cell separation, small substrate radius, and small equivalent-oxide thickness of the gate stack. These results add new constraints to the design of cylindrical junction-less memory technologies.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TED.2013.2264324</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9383 |
| ispartof | IEEE transactions on electron devices, 2013-07, Vol.60 (7), p.2203-2208 |
| issn | 0018-9383 1557-9646 |
| language | eng |
| recordid | cdi_ieee_primary_6527952 |
| source | IEEE Xplore |
| subjects | Applied sciences Arrays Charge-trap memories Design. Technologies. Operation analysis. Testing Dielectrics Doping Electronics Electrostatics erase saturation Exact sciences and technology flash memories Geometry Integrated circuits Integrated circuits by function (including memories and processors) Logic gates semiconductor device modeling Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Substrates |
| title | New Erase Constraint for the Junction-Less Charge-Trap Memory Array in Cylindrical Geometry |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-29T05%3A32%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=New%20Erase%20Constraint%20for%20the%20Junction-Less%20Charge-Trap%20Memory%20Array%20in%20Cylindrical%20Geometry&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Maconi,%20A.&rft.date=2013-07-01&rft.volume=60&rft.issue=7&rft.spage=2203&rft.epage=2208&rft.pages=2203-2208&rft.issn=0018-9383&rft.eissn=1557-9646&rft.coden=IETDAI&rft_id=info:doi/10.1109/TED.2013.2264324&rft_dat=%3Cproquest_RIE%3E3003612451%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1370827038&rft_id=info:pmid/&rft_ieee_id=6527952&rfr_iscdi=true |