An analytical model for evaluating the influence of device parasitics on Cdv/dt induced false turn-on in SiC MOSFETs

Reported here is an analytical methodology for modeling the Cdv/dt induced false turn-on in SiC MOSFETs. A Cdv/dt test circuit is utilized to assess the influence of the parasitic device parameters on the magnitude of the induced gate-source voltage during false turn-on. The effect that each parasitic parameter has on the damping of the SiC MOSFET's drain-source voltage is also evaluated. Experimental results are provided to validate the analytical model. The methods presented here will enable design engineers to project the performance of next generation SiC MOSFETs in high dv/dt circuits like the synchronous buck converter.