Localization of Bugs in Processor Designs Using zamiaCAD Framework

This paper proposes an approach to automatic localization of design errors (bugs) in processor designs based on combining statistical analysis of dynamically covered VHDL code items and static slicing. The approach considers coverage of different VHDL code items including statements, branches and co...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Tepurov, Anton, Tihhomirov, Valentin, Jenihhin, Maksim, Raik, Jaan, Bartsch, Gunter, Escobar, Jorge Hernan Meza, Wuttke, Heinz-Dietrich
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	debug design error localization electronic design automation processor design VHDL
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