Systolic architectures to evaluate polynomials of degree n using the Horner's rule
This paper presents the design of two systolic architectures to evaluate polynomials of degree n considering the Horner's rule. The systolic arrays are based on processing elements that process normalized and non-normalized data. The designed architectures are flexible, parameterized and descri...
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| creator | Forte, G. Espinosa-Duran, J. M. Velasco-Medina, J. |
| description | This paper presents the design of two systolic architectures to evaluate polynomials of degree n considering the Horner's rule. The systolic arrays are based on processing elements that process normalized and non-normalized data. The designed architectures are flexible, parameterized and described by using VHDL. This allows achieving a good trade-off between area, performance and flexibility. The synthesis results show that the proposed architectures can be used as coprocessors for high performance reconfigurable computing. |
| doi_str_mv | 10.1109/LASCAS.2013.6519020 |
| format | Conference Proceeding |
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M. ; Velasco-Medina, J.</creator><creatorcontrib>Forte, G. ; Espinosa-Duran, J. M. ; Velasco-Medina, J.</creatorcontrib><description>This paper presents the design of two systolic architectures to evaluate polynomials of degree n considering the Horner's rule. The systolic arrays are based on processing elements that process normalized and non-normalized data. The designed architectures are flexible, parameterized and described by using VHDL. This allows achieving a good trade-off between area, performance and flexibility. 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The synthesis results show that the proposed architectures can be used as coprocessors for high performance reconfigurable computing.</description><subject>Computer architecture</subject><subject>Digital signal processing</subject><subject>Hardware</subject><subject>Horner's rule</subject><subject>Input variables</subject><subject>Pipelines</subject><subject>Polynomial evaluation</subject><subject>Polynomials</subject><subject>reconfigurable computing</subject><subject>Registers</subject><subject>Systolic architecture</subject><isbn>146734897X</isbn><isbn>9781467348973</isbn><isbn>9781467348997</isbn><isbn>1467348996</isbn><isbn>1467349003</isbn><isbn>9781467349000</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kE1LwzAcxiMiqLOfYJfcPHXmpUmaYynqhIJgFbyNtP13i3TNSFKh397C5unhx_NyeBBaU7KhlOinqqjLot4wQvlGCqoJI1co0SqnmVQ8y7VW1-j-H9T3LUpC-CGELG1Jmb5DH_Ucohtsi41vDzZCGycPAUeH4dcMk4mAT26YR3e0ZgjY9biDvQfAI56CHfc4HgBvnR_BPwbspwEe0E2_RCG56Ap9vTx_ltu0en99K4sqtVSJmIqGsjbPcqIN04Y2nZGNJBwyLQRpBTN6YSGbLO94J7URjVpsKXphlkKn-Aqtz7sWAHYnb4_Gz7vLDfwPKF9RgA</recordid><startdate>201302</startdate><enddate>201302</enddate><creator>Forte, G.</creator><creator>Espinosa-Duran, J. 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M. ; Velasco-Medina, J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-5b12c84809a29a1bda6b603e49550c52a96b656b48d3d69a5b760365f5aa29d73</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Computer architecture</topic><topic>Digital signal processing</topic><topic>Hardware</topic><topic>Horner's rule</topic><topic>Input variables</topic><topic>Pipelines</topic><topic>Polynomial evaluation</topic><topic>Polynomials</topic><topic>reconfigurable computing</topic><topic>Registers</topic><topic>Systolic architecture</topic><toplevel>online_resources</toplevel><creatorcontrib>Forte, G.</creatorcontrib><creatorcontrib>Espinosa-Duran, J. M.</creatorcontrib><creatorcontrib>Velasco-Medina, J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Forte, G.</au><au>Espinosa-Duran, J. M.</au><au>Velasco-Medina, J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Systolic architectures to evaluate polynomials of degree n using the Horner's rule</atitle><btitle>2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)</btitle><stitle>LASCAS</stitle><date>2013-02</date><risdate>2013</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><isbn>146734897X</isbn><isbn>9781467348973</isbn><eisbn>9781467348997</eisbn><eisbn>1467348996</eisbn><eisbn>1467349003</eisbn><eisbn>9781467349000</eisbn><abstract>This paper presents the design of two systolic architectures to evaluate polynomials of degree n considering the Horner's rule. The systolic arrays are based on processing elements that process normalized and non-normalized data. The designed architectures are flexible, parameterized and described by using VHDL. This allows achieving a good trade-off between area, performance and flexibility. The synthesis results show that the proposed architectures can be used as coprocessors for high performance reconfigurable computing.</abstract><pub>IEEE</pub><doi>10.1109/LASCAS.2013.6519020</doi><tpages>4</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Computer architecture Digital signal processing Hardware Horner's rule Input variables Pipelines Polynomial evaluation Polynomials reconfigurable computing Registers Systolic architecture |
| title | Systolic architectures to evaluate polynomials of degree n using the Horner's rule |
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