Development of low power many-core SoC for multimedia applications

Development of low power many-core SoC for multimedia applications

New media processing applications such as image recognition and AR (Augment Reality) have become into practical on embedded systems for automotive, digital-consumer and mobile products. Many-core processors have been proposed to realize much higher performance than multi-core processors. We have dev...

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Hauptverfasser: Miyamori, Takashi, Xu, Hui, Kodaka, Takeshi, Usui, Hiroyuki, Sano, Toru, Tanabe, Jun
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Decoding
H.264
Instruction sets
Low power
Many-core
Multicore processing
Network-on-Chip
Power gating
Super resolution
System-on-chip
VLIW
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creator Miyamori, Takashi
Xu, Hui
Kodaka, Takeshi
Usui, Hiroyuki
Sano, Toru
Tanabe, Jun
description New media processing applications such as image recognition and AR (Augment Reality) have become into practical on embedded systems for automotive, digital-consumer and mobile products. Many-core processors have been proposed to realize much higher performance than multi-core processors. We have developed a low-power many-core SoC for multimedia applications in 40nm CMOS technology. Within a 210mm2 die, two 32-core clusters are integrated with dynamically reconfigurable processors, hardware accelerators, 2-channel DDR3 I/Fs, and other peripherals. Processor cores in the cluster share a 2MB L2 cache connected through a tree-based Network-on-Chip (NoC). Its total peak performance exceeds 1.5TOPS (Tera Operations Per Second). The high scalability and low power consumption are accomplished by parallelized firmware for multimedia applications. It operates the 1080p 30fps H.264 decoding about 400mW and the 4K2K 15fps super resolution under 800mW.
doi_str_mv 10.7873/DATE.2013.164
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subjects Decoding
H.264
Instruction sets
Low power
Many-core
Multicore processing
Network-on-Chip
Power gating
Super resolution
System-on-chip
VLIW
title Development of low power many-core SoC for multimedia applications
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