Process-variation-aware Iddq Diagnois for nano-scale CMOS designs - the firt step

Along with the shrinking CMOS process and rapid design, scaling, both Iddq values and their variation of chips increase. As a result, the defect leakages become less significant when compared to the full-chip currents, making them more in-distinguishable for traditional Iddq diagnosis. Therefore, in...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Chang, Chia-Ling, Wen, Charles H.-P., Bhadra, Jayanta
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	CMOS integrated circuits Integrated circuit modeling Logic gates Random access memory Semiconductor device measurement Testing
Online-Zugang:	Volltext bestellen
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