A 4th order band pass sigma-delta modulator using carry-save for digital IF quadrature modulator
This paper presents a digital intermediate frequency (IF) quadrature modulator realized by a single-bit band pass sigma-delta DAC, in which a pair of single-bit-low-pass sigma-delta digital modulators is used to share the computation for doubling the speed. Fractional-delay interpolation filters are...
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creator | Ruimin Huang Zhen Yan Chaodong Ling Lotze, N. Manoli, Y. |
description | This paper presents a digital intermediate frequency (IF) quadrature modulator realized by a single-bit band pass sigma-delta DAC, in which a pair of single-bit-low-pass sigma-delta digital modulators is used to share the computation for doubling the speed. Fractional-delay interpolation filters are added before the sigma-delta modulators to adjust the interleaved timing relationship between the IQ paths. Carry-save algorithm is used to increase the computation speed in both sigma-delta modulators and interpolation filters, which leads to a speed improvement with little area overhead. The simulation results show that the proposed design can realize a single bit 4th order band pass sigma-delta DAC whose sampling frequency reach hundreds Mhz, and whose SFDR is up to 65 dB. |
doi_str_mv | 10.1109/ICCT.2012.6511390 |
format | Conference Proceeding |
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Fractional-delay interpolation filters are added before the sigma-delta modulators to adjust the interleaved timing relationship between the IQ paths. Carry-save algorithm is used to increase the computation speed in both sigma-delta modulators and interpolation filters, which leads to a speed improvement with little area overhead. The simulation results show that the proposed design can realize a single bit 4th order band pass sigma-delta DAC whose sampling frequency reach hundreds Mhz, and whose SFDR is up to 65 dB.</description><identifier>ISBN: 1467321001</identifier><identifier>ISBN: 9781467321006</identifier><identifier>EISBN: 146732101X</identifier><identifier>EISBN: 9781467321013</identifier><identifier>EISBN: 1467320994</identifier><identifier>EISBN: 9781467320993</identifier><identifier>DOI: 10.1109/ICCT.2012.6511390</identifier><language>eng</language><publisher>IEEE</publisher><subject>2′ complement ; Carry Save ; DSP ; Modulo Arithmetic ; Sigma Delta Modulation</subject><ispartof>2012 IEEE 14th International Conference on Communication Technology, 2012, p.1257-1261</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6511390$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2057,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6511390$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ruimin Huang</creatorcontrib><creatorcontrib>Zhen Yan</creatorcontrib><creatorcontrib>Chaodong Ling</creatorcontrib><creatorcontrib>Lotze, N.</creatorcontrib><creatorcontrib>Manoli, Y.</creatorcontrib><title>A 4th order band pass sigma-delta modulator using carry-save for digital IF quadrature modulator</title><title>2012 IEEE 14th International Conference on Communication Technology</title><addtitle>ICCT</addtitle><description>This paper presents a digital intermediate frequency (IF) quadrature modulator realized by a single-bit band pass sigma-delta DAC, in which a pair of single-bit-low-pass sigma-delta digital modulators is used to share the computation for doubling the speed. Fractional-delay interpolation filters are added before the sigma-delta modulators to adjust the interleaved timing relationship between the IQ paths. Carry-save algorithm is used to increase the computation speed in both sigma-delta modulators and interpolation filters, which leads to a speed improvement with little area overhead. The simulation results show that the proposed design can realize a single bit 4th order band pass sigma-delta DAC whose sampling frequency reach hundreds Mhz, and whose SFDR is up to 65 dB.</description><subject>2′ complement</subject><subject>Carry Save</subject><subject>DSP</subject><subject>Modulo Arithmetic</subject><subject>Sigma Delta Modulation</subject><isbn>1467321001</isbn><isbn>9781467321006</isbn><isbn>146732101X</isbn><isbn>9781467321013</isbn><isbn>1467320994</isbn><isbn>9781467320993</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkE9LAzEUxCMiqLUfQLzkC-z6XjabbI5lsbZQ8FLBW33ZZGtk-8dkV-i3d8FCTzPzg5nDMPaIkCOCeV7W9ToXgCJXJWJh4Irdo1S6EAj4cX0JgLdsmtI3jA5BjfiOfc647L_4ITofuaW940dKiaew3VHmfNcT3x3c0FF_iHxIYb_lDcV4yhL9et6O0IVt6Knjyzn_GchF6ofoL6UHdtNSl_z0rBP2Pn9Z14ts9fa6rGerLKAu-6wpbaONVATOWGgMVMIqqFB47QutW6sslbJsVSWFdrasGmm81AK0MIoqXUzY0_9u8N5vjjHsKJ4250eKPxe_VGs</recordid><startdate>201211</startdate><enddate>201211</enddate><creator>Ruimin Huang</creator><creator>Zhen Yan</creator><creator>Chaodong Ling</creator><creator>Lotze, N.</creator><creator>Manoli, Y.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201211</creationdate><title>A 4th order band pass sigma-delta modulator using carry-save for digital IF quadrature modulator</title><author>Ruimin Huang ; Zhen Yan ; Chaodong Ling ; Lotze, N. ; Manoli, Y.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-c5bc7946a0d9b0c9082b60812e7e377fb6ba545f68427db58c49e47207296a873</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>2′ complement</topic><topic>Carry Save</topic><topic>DSP</topic><topic>Modulo Arithmetic</topic><topic>Sigma Delta Modulation</topic><toplevel>online_resources</toplevel><creatorcontrib>Ruimin Huang</creatorcontrib><creatorcontrib>Zhen Yan</creatorcontrib><creatorcontrib>Chaodong Ling</creatorcontrib><creatorcontrib>Lotze, N.</creatorcontrib><creatorcontrib>Manoli, Y.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ruimin Huang</au><au>Zhen Yan</au><au>Chaodong Ling</au><au>Lotze, N.</au><au>Manoli, Y.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 4th order band pass sigma-delta modulator using carry-save for digital IF quadrature modulator</atitle><btitle>2012 IEEE 14th International Conference on Communication Technology</btitle><stitle>ICCT</stitle><date>2012-11</date><risdate>2012</risdate><spage>1257</spage><epage>1261</epage><pages>1257-1261</pages><isbn>1467321001</isbn><isbn>9781467321006</isbn><eisbn>146732101X</eisbn><eisbn>9781467321013</eisbn><eisbn>1467320994</eisbn><eisbn>9781467320993</eisbn><abstract>This paper presents a digital intermediate frequency (IF) quadrature modulator realized by a single-bit band pass sigma-delta DAC, in which a pair of single-bit-low-pass sigma-delta digital modulators is used to share the computation for doubling the speed. Fractional-delay interpolation filters are added before the sigma-delta modulators to adjust the interleaved timing relationship between the IQ paths. Carry-save algorithm is used to increase the computation speed in both sigma-delta modulators and interpolation filters, which leads to a speed improvement with little area overhead. The simulation results show that the proposed design can realize a single bit 4th order band pass sigma-delta DAC whose sampling frequency reach hundreds Mhz, and whose SFDR is up to 65 dB.</abstract><pub>IEEE</pub><doi>10.1109/ICCT.2012.6511390</doi><tpages>5</tpages></addata></record> |
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subjects | 2′ complement Carry Save DSP Modulo Arithmetic Sigma Delta Modulation |
title | A 4th order band pass sigma-delta modulator using carry-save for digital IF quadrature modulator |
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