Comparison of fast radix 2 ACS with adaptive fast radix 2 ACS in Viterbi Decoder
Adaptive Viterbi decoder is used for decoding codes of long constraint length, where as viterbi decoder is used for decoding short constraint lengths. In order to minimize power consumption and BER, we have implemented FastRadix 2 ACS in Viterbi decoder and Adaptive Viterbi decoder. The area consump...
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| creator | Bobby, N. D. Srivatsa, S. K. Kishore, L. Rajiv, A. Suresh, S. S. |
| description | Adaptive Viterbi decoder is used for decoding codes of long constraint length, where as viterbi decoder is used for decoding short constraint lengths. In order to minimize power consumption and BER, we have implemented FastRadix 2 ACS in Viterbi decoder and Adaptive Viterbi decoder. The area consumption was more in Viterbi compared to Adaptive Viterbi decoder. But the power utilization reduced drastically to 20% where as in Viterbi decoder the power consumed was 80%. In our previous work we have implemented Adaptive fast ACS, Adaptive Radix2 acs in Viterbi decoder. But the experimental result proves power consumption is less in Adaptive FastRadix 2 ACS in Viterbi decoder than FastRadix 2 ACS in Viterbi decoder. |
| doi_str_mv | 10.1109/ICEVENT.2013.6496563 |
| format | Conference Proceeding |
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In our previous work we have implemented Adaptive fast ACS, Adaptive Radix2 acs in Viterbi decoder. But the experimental result proves power consumption is less in Adaptive FastRadix 2 ACS in Viterbi decoder than FastRadix 2 ACS in Viterbi decoder.</description><subject>ACS</subject><subject>AVD</subject><subject>Bit error rate</subject><subject>Decoding</subject><subject>Fast Radix 2 Acs</subject><subject>Fastacs</subject><subject>FPGA</subject><subject>IP networks</subject><subject>Logic gates</subject><subject>Measurement</subject><subject>Radix 2 ACS</subject><subject>Very large scale integration</subject><subject>Viterbi algorithm</subject><subject>Viterbi Decoding</subject><subject>VLSI</subject><isbn>1467353000</isbn><isbn>9781467353007</isbn><isbn>9781467352994</isbn><isbn>1467352993</isbn><isbn>9781467353014</isbn><isbn>1467353019</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNplUNtKw0AUXBFBrfkCfdgfSDx7y_Y8lhi1UFSw9rXsbk5wxTZhE7z8vYH2zYdhZpjDYRjGbgQUQgDeLqt6Uz-tCwlCFaXG0pTqhGVo50KXVhmJqE_Z5cEoADhn2TB8TALQSoXmgr1U3a53KQ7dnnctb90w8uSa-MMlX1Sv_DuO79w1rh_jF_2P455v4kjJR35HoWsoXbGz1n0OlB15xt7u63X1mK-eH5bVYpVHYc2Yk5DGqsaXBoJTBtF66QKCAjUVDSEQeK9LNR0BOa1lgwLthOBhTkhqxq4PfyMRbfsUdy79bo8jqD_hYU5z</recordid><startdate>201301</startdate><enddate>201301</enddate><creator>Bobby, N. D.</creator><creator>Srivatsa, S. K.</creator><creator>Kishore, L.</creator><creator>Rajiv, A.</creator><creator>Suresh, S. S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201301</creationdate><title>Comparison of fast radix 2 ACS with adaptive fast radix 2 ACS in Viterbi Decoder</title><author>Bobby, N. D. ; Srivatsa, S. K. ; Kishore, L. ; Rajiv, A. ; Suresh, S. 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S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bobby, N. D.</au><au>Srivatsa, S. K.</au><au>Kishore, L.</au><au>Rajiv, A.</au><au>Suresh, S. S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Comparison of fast radix 2 ACS with adaptive fast radix 2 ACS in Viterbi Decoder</atitle><btitle>2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)</btitle><stitle>ICEVENT</stitle><date>2013-01</date><risdate>2013</risdate><spage>1</spage><epage>5</epage><pages>1-5</pages><isbn>1467353000</isbn><isbn>9781467353007</isbn><eisbn>9781467352994</eisbn><eisbn>1467352993</eisbn><eisbn>9781467353014</eisbn><eisbn>1467353019</eisbn><abstract>Adaptive Viterbi decoder is used for decoding codes of long constraint length, where as viterbi decoder is used for decoding short constraint lengths. In order to minimize power consumption and BER, we have implemented FastRadix 2 ACS in Viterbi decoder and Adaptive Viterbi decoder. The area consumption was more in Viterbi compared to Adaptive Viterbi decoder. But the power utilization reduced drastically to 20% where as in Viterbi decoder the power consumed was 80%. In our previous work we have implemented Adaptive fast ACS, Adaptive Radix2 acs in Viterbi decoder. But the experimental result proves power consumption is less in Adaptive FastRadix 2 ACS in Viterbi decoder than FastRadix 2 ACS in Viterbi decoder.</abstract><pub>IEEE</pub><doi>10.1109/ICEVENT.2013.6496563</doi><tpages>5</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | ACS AVD Bit error rate Decoding Fast Radix 2 Acs Fastacs FPGA IP networks Logic gates Measurement Radix 2 ACS Very large scale integration Viterbi algorithm Viterbi Decoding VLSI |
| title | Comparison of fast radix 2 ACS with adaptive fast radix 2 ACS in Viterbi Decoder |
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