Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology

This paper presents an IEEE 802.11n Low-Density Parity-Check (LDPC) decoder implemented in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FDSOI), and demonstrates the performance gains of this circuit vs. 28nm LP high-κ metal-gate CMOS bulk technology. It also introduces extended body bias (B...

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Hauptverfasser: Flatresse, P., Giraud, B., Noel, J., Pelloux-Prayer, B., Giner, F., Arora, D., Arnaud, F., Planes, N., Le Coz, J., Thomas, O., Engels, S., Cesana, G., Wilson, R., Urard, P.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Decoding
Electrostatics
Frequency measurement
IEEE 802.11n Standard
Logic gates
Parity check codes
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Beschreibung
Zusammenfassung:This paper presents an IEEE 802.11n Low-Density Parity-Check (LDPC) decoder implemented in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FDSOI), and demonstrates the performance gains of this circuit vs. 28nm LP high-κ metal-gate CMOS bulk technology. It also introduces extended body bias (BB) design techniques to take advantage of specific features of the UTBB technology to overcome the +/-300mV BB range limitation of conventional bulk technologies [1].
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2013.6487798