A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS

High-performance computing (HPC) systems demand aggressive scaling of memory and I/O to achieve multiple terabits/sec of bandwidth. Minimizing I/O cost, area and power are crucial to achieving a practically realizable system with such large bandwidth. To meet these needs, we developed a low-power de...

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Bibliographische Detailangaben

Hauptverfasser:	Mansuri, M., Jaussi, J. E., Kennedy, J. T., Hsueh, T., Shekhar, S., Balamurugan, G., O'Mahony, F., Roberts, C., Mooney, R., Casper, B.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Aggregates Bandwidth Clocks CMOS integrated circuits Connectors Integrated circuit interconnections Solid state circuits
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