An all-digital PLL using random modulation for SSC generation in 65nm CMOS

This paper introduces a digital PLL which uses high-frequency random modulation (RM), as opposed to low-frequency periodic modulation, to generate a spread spectrum clock (SSC). The implementation is straightforward and reduces accumulated jitter substantially (by a factor of 8 in our implementation...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Da Dalt, N., Pridnig, P., Grollitsch, W.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks Electromagnetic interference Frequency modulation Jitter Phase locked loops Temperature measurement
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