32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS

In next-generation communication standards, such as OIF CEI-28G-SR and CEI-56G-VSR, the data rate has to be doubled or quadrupled compared to the current standards. Though transceivers for a data rate over 25Gb/s have been reported [1-3], designing clock-generating circuits for the receiver front-en...

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Bibliographische Detailangaben

Hauptverfasser:	Doi, Y., Shibasaki, T., Danjo, T., Chaivipas, W., Hashida, T., Miyaoka, H., Hoshino, M., Koyanagi, Y., Yamamoto, T., Tsukamoto, S., Tamura, H.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Capacitors Clocks CMOS integrated circuits Decision feedback equalizers Interpolation Receivers Transceivers
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