Optimized MAC unit design
In this paper, a new multiplier design is proposed which reduces the number of partial products by 25%. This multiplier has been used with different adders available in literature to implement multiplier accumulator (MAC) unit and parameters such as propagation delay, power consumed and area occupie...
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| creator | Deepak, S. Kailath, B. J. |
| description | In this paper, a new multiplier design is proposed which reduces the number of partial products by 25%. This multiplier has been used with different adders available in literature to implement multiplier accumulator (MAC) unit and parameters such as propagation delay, power consumed and area occupied have been compared in each case. From the results, Kogg tone adder has been chosen as it provided optimum values of delay and power dissipation. Later, the results obtained have been compared with that of other multipliers and it has been observed that the proposed multiplier has the lowest propagation delay when compared with Array and Booth multipliers. |
| doi_str_mv | 10.1109/EDSSC.2012.6482843 |
| format | Conference Proceeding |
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J.</creator><creatorcontrib>Deepak, S. ; Kailath, B. J.</creatorcontrib><description>In this paper, a new multiplier design is proposed which reduces the number of partial products by 25%. This multiplier has been used with different adders available in literature to implement multiplier accumulator (MAC) unit and parameters such as propagation delay, power consumed and area occupied have been compared in each case. From the results, Kogg tone adder has been chosen as it provided optimum values of delay and power dissipation. Later, the results obtained have been compared with that of other multipliers and it has been observed that the proposed multiplier has the lowest propagation delay when compared with Array and Booth multipliers.</description><identifier>ISBN: 9781467356947</identifier><identifier>ISBN: 1467356948</identifier><identifier>EISBN: 1467356964</identifier><identifier>EISBN: 9781467356961</identifier><identifier>EISBN: 1467356956</identifier><identifier>EISBN: 9781467356954</identifier><identifier>DOI: 10.1109/EDSSC.2012.6482843</identifier><language>eng</language><publisher>IEEE</publisher><subject>Adders ; Arrays ; Educational institutions ; MAC Unit ; multiplier ; Power demand ; Power dissipation ; Propagation delay ; RTL Compiler ; Simulation</subject><ispartof>2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC), 2012, p.1-4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6482843$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6482843$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Deepak, S.</creatorcontrib><creatorcontrib>Kailath, B. J.</creatorcontrib><title>Optimized MAC unit design</title><title>2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC)</title><addtitle>EDSSC</addtitle><description>In this paper, a new multiplier design is proposed which reduces the number of partial products by 25%. This multiplier has been used with different adders available in literature to implement multiplier accumulator (MAC) unit and parameters such as propagation delay, power consumed and area occupied have been compared in each case. From the results, Kogg tone adder has been chosen as it provided optimum values of delay and power dissipation. Later, the results obtained have been compared with that of other multipliers and it has been observed that the proposed multiplier has the lowest propagation delay when compared with Array and Booth multipliers.</description><subject>Adders</subject><subject>Arrays</subject><subject>Educational institutions</subject><subject>MAC Unit</subject><subject>multiplier</subject><subject>Power demand</subject><subject>Power dissipation</subject><subject>Propagation delay</subject><subject>RTL Compiler</subject><subject>Simulation</subject><isbn>9781467356947</isbn><isbn>1467356948</isbn><isbn>1467356964</isbn><isbn>9781467356961</isbn><isbn>1467356956</isbn><isbn>9781467356954</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1j7tOAzEQAI0QEhDuA4DmfuAuu2t7bZfRER5SohSBOnLOa2REoih3FPD1FIRqNM1Io9QdQosIYTp_WK-7lgCpZePJG32mrtGw05YDm3NVBef_3bhLVQ3DBwBgYMear9Tt6jCWXfmRVC9nXf21L2OdZCjv-xt1kePnINWJE_X2OH_tnpvF6umlmy2ags6OTY55i9kEk0CzQ-KeSROAjxxkSyQ29Qalt2QxkbUhSfLRepEcQ5-Nnqj7v24Rkc3hWHbx-L053ehfh5o8FQ</recordid><startdate>201212</startdate><enddate>201212</enddate><creator>Deepak, S.</creator><creator>Kailath, B. J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201212</creationdate><title>Optimized MAC unit design</title><author>Deepak, S. ; Kailath, B. J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-fafb1f494d0367126c6232008a69eb22e5dc41ec5251d2559ded8a58eefa9cf43</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Adders</topic><topic>Arrays</topic><topic>Educational institutions</topic><topic>MAC Unit</topic><topic>multiplier</topic><topic>Power demand</topic><topic>Power dissipation</topic><topic>Propagation delay</topic><topic>RTL Compiler</topic><topic>Simulation</topic><toplevel>online_resources</toplevel><creatorcontrib>Deepak, S.</creatorcontrib><creatorcontrib>Kailath, B. J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Deepak, S.</au><au>Kailath, B. J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Optimized MAC unit design</atitle><btitle>2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC)</btitle><stitle>EDSSC</stitle><date>2012-12</date><risdate>2012</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><isbn>9781467356947</isbn><isbn>1467356948</isbn><eisbn>1467356964</eisbn><eisbn>9781467356961</eisbn><eisbn>1467356956</eisbn><eisbn>9781467356954</eisbn><abstract>In this paper, a new multiplier design is proposed which reduces the number of partial products by 25%. This multiplier has been used with different adders available in literature to implement multiplier accumulator (MAC) unit and parameters such as propagation delay, power consumed and area occupied have been compared in each case. From the results, Kogg tone adder has been chosen as it provided optimum values of delay and power dissipation. Later, the results obtained have been compared with that of other multipliers and it has been observed that the proposed multiplier has the lowest propagation delay when compared with Array and Booth multipliers.</abstract><pub>IEEE</pub><doi>10.1109/EDSSC.2012.6482843</doi><tpages>4</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Adders Arrays Educational institutions MAC Unit multiplier Power demand Power dissipation Propagation delay RTL Compiler Simulation |
| title | Optimized MAC unit design |
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