High resolution and frame rate image signal processor array design for 3-D imager
This paper presents a high resolution and frame rate image signal processor (ISP) array design for three-dimensional (3-D) imager. Based on the through-silicon via (TSV) technology, the short connections of the 3-D integrated circuit (IC) can improve the performance and density. Hence, the 3-D image...
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| creator | Chang-Hsin Cheng Hsien-Ching Hsieh Tso-Yi Fan Wei-Xiang Tang Chung-Kai Liu Po-Han Huang |
| description | This paper presents a high resolution and frame rate image signal processor (ISP) array design for three-dimensional (3-D) imager. Based on the through-silicon via (TSV) technology, the short connections of the 3-D integrated circuit (IC) can improve the performance and density. Hence, the 3-D imager is the best solution for high throughput image capture or video recorder applications. The proposed ISP array is based on high resolution CMOS image sensor (CIS) and analog-to-digital converter (ADC) array to achieve three mega pixels (2048×1536) at 100 frames per second in 3-D imager. The architectural simulation results show the proposed design costs area 9000× 7000 μm 2 , average power 0.79 W and throughput 6.93 bps to verify the feasibility of high resolution and frame rate application for 3-D imager. |
| doi_str_mv | 10.1109/ISPACS.2012.6473588 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6473588</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6473588</ieee_id><sourcerecordid>6473588</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-65e79377db1fdacd7c47a9eb97aceaca156f097138d3386b357ea03d70d845d93</originalsourceid><addsrcrecordid>eNo1UMtOwzAQNEJIQMkX9OIfSLHjOGsfq_BopUqACudqE2-CUZpUdjj070nVctqZ3XlIy9hcioWUwj6ut-_LcrvIhMwWRQ5KG3PF7mVeTFAYaa5ZYsH8c2VvWRLjjxBichcqE3fsY-Xbbx4oDt3v6IeeY-94E3BPPOBI3O-xJR5922PHD2GoKcYhcAwBj9zR6cCbaaHSp7M2PLCbBrtIyWXO2NfL82e5Sjdvr-tyuUm9BD2mhSawCsBVsnFYO6hzQEuVBawJa5S6aIQFqYxTyhSV0kAolAPhTK6dVTM2P-d6ItodwtQejrvLF9QfRFpREg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>High resolution and frame rate image signal processor array design for 3-D imager</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Chang-Hsin Cheng ; Hsien-Ching Hsieh ; Tso-Yi Fan ; Wei-Xiang Tang ; Chung-Kai Liu ; Po-Han Huang</creator><creatorcontrib>Chang-Hsin Cheng ; Hsien-Ching Hsieh ; Tso-Yi Fan ; Wei-Xiang Tang ; Chung-Kai Liu ; Po-Han Huang</creatorcontrib><description>This paper presents a high resolution and frame rate image signal processor (ISP) array design for three-dimensional (3-D) imager. Based on the through-silicon via (TSV) technology, the short connections of the 3-D integrated circuit (IC) can improve the performance and density. Hence, the 3-D imager is the best solution for high throughput image capture or video recorder applications. The proposed ISP array is based on high resolution CMOS image sensor (CIS) and analog-to-digital converter (ADC) array to achieve three mega pixels (2048×1536) at 100 frames per second in 3-D imager. The architectural simulation results show the proposed design costs area 9000× 7000 μm 2 , average power 0.79 W and throughput 6.93 bps to verify the feasibility of high resolution and frame rate application for 3-D imager.</description><identifier>ISBN: 9781467350839</identifier><identifier>ISBN: 1467350834</identifier><identifier>EISBN: 1467350818</identifier><identifier>EISBN: 9781467350822</identifier><identifier>EISBN: 1467350826</identifier><identifier>EISBN: 9781467350815</identifier><identifier>DOI: 10.1109/ISPACS.2012.6473588</identifier><language>eng</language><publisher>IEEE</publisher><subject>3-D imager ; Arrays ; Bridge circuits ; frame rate ; high resolution ; Image resolution ; Integrated circuits ; ISP array ; Switching circuits ; Throughput</subject><ispartof>2012 International Symposium on Intelligent Signal Processing and Communications Systems, 2012, p.735-739</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6473588$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,778,782,787,788,2054,27908,54903</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6473588$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chang-Hsin Cheng</creatorcontrib><creatorcontrib>Hsien-Ching Hsieh</creatorcontrib><creatorcontrib>Tso-Yi Fan</creatorcontrib><creatorcontrib>Wei-Xiang Tang</creatorcontrib><creatorcontrib>Chung-Kai Liu</creatorcontrib><creatorcontrib>Po-Han Huang</creatorcontrib><title>High resolution and frame rate image signal processor array design for 3-D imager</title><title>2012 International Symposium on Intelligent Signal Processing and Communications Systems</title><addtitle>ISPACS</addtitle><description>This paper presents a high resolution and frame rate image signal processor (ISP) array design for three-dimensional (3-D) imager. Based on the through-silicon via (TSV) technology, the short connections of the 3-D integrated circuit (IC) can improve the performance and density. Hence, the 3-D imager is the best solution for high throughput image capture or video recorder applications. The proposed ISP array is based on high resolution CMOS image sensor (CIS) and analog-to-digital converter (ADC) array to achieve three mega pixels (2048×1536) at 100 frames per second in 3-D imager. The architectural simulation results show the proposed design costs area 9000× 7000 μm 2 , average power 0.79 W and throughput 6.93 bps to verify the feasibility of high resolution and frame rate application for 3-D imager.</description><subject>3-D imager</subject><subject>Arrays</subject><subject>Bridge circuits</subject><subject>frame rate</subject><subject>high resolution</subject><subject>Image resolution</subject><subject>Integrated circuits</subject><subject>ISP array</subject><subject>Switching circuits</subject><subject>Throughput</subject><isbn>9781467350839</isbn><isbn>1467350834</isbn><isbn>1467350818</isbn><isbn>9781467350822</isbn><isbn>1467350826</isbn><isbn>9781467350815</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1UMtOwzAQNEJIQMkX9OIfSLHjOGsfq_BopUqACudqE2-CUZpUdjj070nVctqZ3XlIy9hcioWUwj6ut-_LcrvIhMwWRQ5KG3PF7mVeTFAYaa5ZYsH8c2VvWRLjjxBichcqE3fsY-Xbbx4oDt3v6IeeY-94E3BPPOBI3O-xJR5922PHD2GoKcYhcAwBj9zR6cCbaaHSp7M2PLCbBrtIyWXO2NfL82e5Sjdvr-tyuUm9BD2mhSawCsBVsnFYO6hzQEuVBawJa5S6aIQFqYxTyhSV0kAolAPhTK6dVTM2P-d6ItodwtQejrvLF9QfRFpREg</recordid><startdate>201211</startdate><enddate>201211</enddate><creator>Chang-Hsin Cheng</creator><creator>Hsien-Ching Hsieh</creator><creator>Tso-Yi Fan</creator><creator>Wei-Xiang Tang</creator><creator>Chung-Kai Liu</creator><creator>Po-Han Huang</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201211</creationdate><title>High resolution and frame rate image signal processor array design for 3-D imager</title><author>Chang-Hsin Cheng ; Hsien-Ching Hsieh ; Tso-Yi Fan ; Wei-Xiang Tang ; Chung-Kai Liu ; Po-Han Huang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-65e79377db1fdacd7c47a9eb97aceaca156f097138d3386b357ea03d70d845d93</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>3-D imager</topic><topic>Arrays</topic><topic>Bridge circuits</topic><topic>frame rate</topic><topic>high resolution</topic><topic>Image resolution</topic><topic>Integrated circuits</topic><topic>ISP array</topic><topic>Switching circuits</topic><topic>Throughput</topic><toplevel>online_resources</toplevel><creatorcontrib>Chang-Hsin Cheng</creatorcontrib><creatorcontrib>Hsien-Ching Hsieh</creatorcontrib><creatorcontrib>Tso-Yi Fan</creatorcontrib><creatorcontrib>Wei-Xiang Tang</creatorcontrib><creatorcontrib>Chung-Kai Liu</creatorcontrib><creatorcontrib>Po-Han Huang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chang-Hsin Cheng</au><au>Hsien-Ching Hsieh</au><au>Tso-Yi Fan</au><au>Wei-Xiang Tang</au><au>Chung-Kai Liu</au><au>Po-Han Huang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>High resolution and frame rate image signal processor array design for 3-D imager</atitle><btitle>2012 International Symposium on Intelligent Signal Processing and Communications Systems</btitle><stitle>ISPACS</stitle><date>2012-11</date><risdate>2012</risdate><spage>735</spage><epage>739</epage><pages>735-739</pages><isbn>9781467350839</isbn><isbn>1467350834</isbn><eisbn>1467350818</eisbn><eisbn>9781467350822</eisbn><eisbn>1467350826</eisbn><eisbn>9781467350815</eisbn><abstract>This paper presents a high resolution and frame rate image signal processor (ISP) array design for three-dimensional (3-D) imager. Based on the through-silicon via (TSV) technology, the short connections of the 3-D integrated circuit (IC) can improve the performance and density. Hence, the 3-D imager is the best solution for high throughput image capture or video recorder applications. The proposed ISP array is based on high resolution CMOS image sensor (CIS) and analog-to-digital converter (ADC) array to achieve three mega pixels (2048×1536) at 100 frames per second in 3-D imager. The architectural simulation results show the proposed design costs area 9000× 7000 μm 2 , average power 0.79 W and throughput 6.93 bps to verify the feasibility of high resolution and frame rate application for 3-D imager.</abstract><pub>IEEE</pub><doi>10.1109/ISPACS.2012.6473588</doi><tpages>5</tpages></addata></record> |
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| identifier | ISBN: 9781467350839 |
| ispartof | 2012 International Symposium on Intelligent Signal Processing and Communications Systems, 2012, p.735-739 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | 3-D imager Arrays Bridge circuits frame rate high resolution Image resolution Integrated circuits ISP array Switching circuits Throughput |
| title | High resolution and frame rate image signal processor array design for 3-D imager |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T17%3A09%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=High%20resolution%20and%20frame%20rate%20image%20signal%20processor%20array%20design%20for%203-D%20imager&rft.btitle=2012%20International%20Symposium%20on%20Intelligent%20Signal%20Processing%20and%20Communications%20Systems&rft.au=Chang-Hsin%20Cheng&rft.date=2012-11&rft.spage=735&rft.epage=739&rft.pages=735-739&rft.isbn=9781467350839&rft.isbn_list=1467350834&rft_id=info:doi/10.1109/ISPACS.2012.6473588&rft_dat=%3Cieee_6IE%3E6473588%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1467350818&rft.eisbn_list=9781467350822&rft.eisbn_list=1467350826&rft.eisbn_list=9781467350815&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6473588&rfr_iscdi=true |