Montgomery modular exponentiation on FPGA

Modular exponentiation is the main operation of RSA-based public-key cryptosystems. It is implemented by repeated modular multiplications which are time consuming for large operands. Accelerating the RSA requires reducing the number of modular multiplications, thus reducing the time to perform one modular multiplication. In this paper, we present an architecture designed to implement a fast modular exponentiation using the right to left binary method (R-L), which allows the parallel execution of modular operations "squares and multiplications". The fast modular multiplication used is based on Montgomery algorithm. This architecture has been implemented on an FPGA circuit of Xilinx, the XC4VLX25-12ff668 of Virtex-4. The implementation results showed that the architecture computing 1024 bits modular exponentiation presents good performance in terms of speed and occupied area with the possibility of changing the key size by reprogramming the FPGA according to the security level and the performance to attain.