Geometrical impact on RF performances of broadband ESD self protected transmission line in advanced CMOS technologies
Advanced CMOS technologies provide an easy way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharge (ESD) issues become more significant. Unfortunately, parasitic capacitance of the ESD protection limits the operating bandw...
Gespeichert in:
| Hauptverfasser: | , , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 186 |
|---|---|
| container_issue | |
| container_start_page | 183 |
| container_title | |
| container_volume | |
| creator | Tekfouy Lim Jimenez, J. Benech, P. Fournier, J. Heitz, B. Galy, P. |
| description | Advanced CMOS technologies provide an easy way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharge (ESD) issues become more significant. Unfortunately, parasitic capacitance of the ESD protection limits the operating bandwidth of the RFICs. The size (i.e. die area) of ESD protection is also of concern in RFICs. This paper presents results of transmission line with ESD protection devices able to be implemented in an I/O pad in advanced CMOS technologies. |
| doi_str_mv | 10.1109/IIRW.2012.6468951 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6468951</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6468951</ieee_id><sourcerecordid>6468951</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-909148e2d08af2c9966c1801d17f48d52d8e9905b86b4721bae8fe4ee87723133</originalsourceid><addsrcrecordid>eNo9kMtOwzAURM1LopR-AGLjH0jxtZ3YXqLSlkpFlVoQy8qJb8AoiSM7IPH3FFGxmsXMOYsh5AbYFICZu9Vq-zrlDPi0kIU2OZyQK5CFElzlIE_JiAslM81EcfZfSMPPyQiMYJnWEi7JJKUPxthBWAhgI_K5xNDiEH1lG-rb3lYDDR3dLmiPsQ6xtV2FiYaaljFYV9rO0fnugSZsatrHMGA1oKNDtF1qfUr-ADe-Q-o7at3XL-3o7Gmzo4flexea8OYxXZOL2jYJJ8cck5fF_Hn2mK03y9Xsfp15UPmQGWZAauSOaVvzypiiqEAzcKBqqV3OnUZjWF7qopSKQ2lR1ygRtVJcgBBjcvvn9Yi476NvbfzeH-8TP7KEYBc</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Geometrical impact on RF performances of broadband ESD self protected transmission line in advanced CMOS technologies</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Tekfouy Lim ; Jimenez, J. ; Benech, P. ; Fournier, J. ; Heitz, B. ; Galy, P.</creator><creatorcontrib>Tekfouy Lim ; Jimenez, J. ; Benech, P. ; Fournier, J. ; Heitz, B. ; Galy, P.</creatorcontrib><description>Advanced CMOS technologies provide an easy way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharge (ESD) issues become more significant. Unfortunately, parasitic capacitance of the ESD protection limits the operating bandwidth of the RFICs. The size (i.e. die area) of ESD protection is also of concern in RFICs. This paper presents results of transmission line with ESD protection devices able to be implemented in an I/O pad in advanced CMOS technologies.</description><identifier>ISSN: 1930-8841</identifier><identifier>ISBN: 1467327492</identifier><identifier>ISBN: 9781467327497</identifier><identifier>EISSN: 2374-8036</identifier><identifier>EISBN: 1467327514</identifier><identifier>EISBN: 9781467327510</identifier><identifier>EISBN: 9781467327527</identifier><identifier>EISBN: 1467327522</identifier><identifier>DOI: 10.1109/IIRW.2012.6468951</identifier><language>eng</language><publisher>IEEE</publisher><subject>Broadband communication ; CMOS integrated circuits ; CMOS technology ; Electrostatic discharges ; Impedance ; Radio frequency ; Transmission line measurements</subject><ispartof>2012 IEEE International Integrated Reliability Workshop Final Report, 2012, p.183-186</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6468951$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>310,311,781,785,790,791,2059,27927,54922</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6468951$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Tekfouy Lim</creatorcontrib><creatorcontrib>Jimenez, J.</creatorcontrib><creatorcontrib>Benech, P.</creatorcontrib><creatorcontrib>Fournier, J.</creatorcontrib><creatorcontrib>Heitz, B.</creatorcontrib><creatorcontrib>Galy, P.</creatorcontrib><title>Geometrical impact on RF performances of broadband ESD self protected transmission line in advanced CMOS technologies</title><title>2012 IEEE International Integrated Reliability Workshop Final Report</title><addtitle>IIRW</addtitle><description>Advanced CMOS technologies provide an easy way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharge (ESD) issues become more significant. Unfortunately, parasitic capacitance of the ESD protection limits the operating bandwidth of the RFICs. The size (i.e. die area) of ESD protection is also of concern in RFICs. This paper presents results of transmission line with ESD protection devices able to be implemented in an I/O pad in advanced CMOS technologies.</description><subject>Broadband communication</subject><subject>CMOS integrated circuits</subject><subject>CMOS technology</subject><subject>Electrostatic discharges</subject><subject>Impedance</subject><subject>Radio frequency</subject><subject>Transmission line measurements</subject><issn>1930-8841</issn><issn>2374-8036</issn><isbn>1467327492</isbn><isbn>9781467327497</isbn><isbn>1467327514</isbn><isbn>9781467327510</isbn><isbn>9781467327527</isbn><isbn>1467327522</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9kMtOwzAURM1LopR-AGLjH0jxtZ3YXqLSlkpFlVoQy8qJb8AoiSM7IPH3FFGxmsXMOYsh5AbYFICZu9Vq-zrlDPi0kIU2OZyQK5CFElzlIE_JiAslM81EcfZfSMPPyQiMYJnWEi7JJKUPxthBWAhgI_K5xNDiEH1lG-rb3lYDDR3dLmiPsQ6xtV2FiYaaljFYV9rO0fnugSZsatrHMGA1oKNDtF1qfUr-ADe-Q-o7at3XL-3o7Gmzo4flexea8OYxXZOL2jYJJ8cck5fF_Hn2mK03y9Xsfp15UPmQGWZAauSOaVvzypiiqEAzcKBqqV3OnUZjWF7qopSKQ2lR1ygRtVJcgBBjcvvn9Yi476NvbfzeH-8TP7KEYBc</recordid><startdate>201210</startdate><enddate>201210</enddate><creator>Tekfouy Lim</creator><creator>Jimenez, J.</creator><creator>Benech, P.</creator><creator>Fournier, J.</creator><creator>Heitz, B.</creator><creator>Galy, P.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201210</creationdate><title>Geometrical impact on RF performances of broadband ESD self protected transmission line in advanced CMOS technologies</title><author>Tekfouy Lim ; Jimenez, J. ; Benech, P. ; Fournier, J. ; Heitz, B. ; Galy, P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-909148e2d08af2c9966c1801d17f48d52d8e9905b86b4721bae8fe4ee87723133</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Broadband communication</topic><topic>CMOS integrated circuits</topic><topic>CMOS technology</topic><topic>Electrostatic discharges</topic><topic>Impedance</topic><topic>Radio frequency</topic><topic>Transmission line measurements</topic><toplevel>online_resources</toplevel><creatorcontrib>Tekfouy Lim</creatorcontrib><creatorcontrib>Jimenez, J.</creatorcontrib><creatorcontrib>Benech, P.</creatorcontrib><creatorcontrib>Fournier, J.</creatorcontrib><creatorcontrib>Heitz, B.</creatorcontrib><creatorcontrib>Galy, P.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tekfouy Lim</au><au>Jimenez, J.</au><au>Benech, P.</au><au>Fournier, J.</au><au>Heitz, B.</au><au>Galy, P.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Geometrical impact on RF performances of broadband ESD self protected transmission line in advanced CMOS technologies</atitle><btitle>2012 IEEE International Integrated Reliability Workshop Final Report</btitle><stitle>IIRW</stitle><date>2012-10</date><risdate>2012</risdate><spage>183</spage><epage>186</epage><pages>183-186</pages><issn>1930-8841</issn><eissn>2374-8036</eissn><isbn>1467327492</isbn><isbn>9781467327497</isbn><eisbn>1467327514</eisbn><eisbn>9781467327510</eisbn><eisbn>9781467327527</eisbn><eisbn>1467327522</eisbn><abstract>Advanced CMOS technologies provide an easy way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharge (ESD) issues become more significant. Unfortunately, parasitic capacitance of the ESD protection limits the operating bandwidth of the RFICs. The size (i.e. die area) of ESD protection is also of concern in RFICs. This paper presents results of transmission line with ESD protection devices able to be implemented in an I/O pad in advanced CMOS technologies.</abstract><pub>IEEE</pub><doi>10.1109/IIRW.2012.6468951</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1930-8841 |
| ispartof | 2012 IEEE International Integrated Reliability Workshop Final Report, 2012, p.183-186 |
| issn | 1930-8841 2374-8036 |
| language | eng |
| recordid | cdi_ieee_primary_6468951 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Broadband communication CMOS integrated circuits CMOS technology Electrostatic discharges Impedance Radio frequency Transmission line measurements |
| title | Geometrical impact on RF performances of broadband ESD self protected transmission line in advanced CMOS technologies |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-17T16%3A26%3A48IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Geometrical%20impact%20on%20RF%20performances%20of%20broadband%20ESD%20self%20protected%20transmission%20line%20in%20advanced%20CMOS%20technologies&rft.btitle=2012%20IEEE%20International%20Integrated%20Reliability%20Workshop%20Final%20Report&rft.au=Tekfouy%20Lim&rft.date=2012-10&rft.spage=183&rft.epage=186&rft.pages=183-186&rft.issn=1930-8841&rft.eissn=2374-8036&rft.isbn=1467327492&rft.isbn_list=9781467327497&rft_id=info:doi/10.1109/IIRW.2012.6468951&rft_dat=%3Cieee_6IE%3E6468951%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1467327514&rft.eisbn_list=9781467327510&rft.eisbn_list=9781467327527&rft.eisbn_list=1467327522&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6468951&rfr_iscdi=true |