The optimization and application of DDR controller based on multi-core system

An application to improve the performance of DDR memory controller based on network processor is described in this paper. The DDR memory controller is designed to prefetch instructions to get the address relationship of consecutive instructions in advance. The controller can be able to utilizing the...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Hui-Hui Zou, Pei-Jun Ma, Jiang-Yi Shi, Kang Li, Zhi-Xiong Di
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Field programmable gate arrays Memory architecture Memory management Optimization Prefetching Process control Timing
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