Flip-flop design using novel pulse generation technique
In this paper, new flip-flop topologies for low power and high-speed digital designs are presented. A novel technique is used to generate a special clock-pulse wave (internally or externally) for flip-flop circuits. This technique shows better characteristics compared to existing techniques in terms...
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| creator | Moradi, F. Wisland, D. Kargaard Madsen, Jens Mahmoodi, H. |
| description | In this paper, new flip-flop topologies for low power and high-speed digital designs are presented. A novel technique is used to generate a special clock-pulse wave (internally or externally) for flip-flop circuits. This technique shows better characteristics compared to existing techniques in terms of delay and power. The generated pulse is applied to different flip-flop topologies to show the efficacy of the proposed technique on power and speed. Simulation results show improvement in setup time compared to their counterparts. Furthermore, at least 20% improvement in power consumption is observed by utilizing the proposed pulse-generator technique. IBM 65nm Models are used for simulation using CADENCE and Synopsys tools. |
| doi_str_mv | 10.1109/ICECS.2012.6463633 |
| format | Conference Proceeding |
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A novel technique is used to generate a special clock-pulse wave (internally or externally) for flip-flop circuits. This technique shows better characteristics compared to existing techniques in terms of delay and power. The generated pulse is applied to different flip-flop topologies to show the efficacy of the proposed technique on power and speed. Simulation results show improvement in setup time compared to their counterparts. Furthermore, at least 20% improvement in power consumption is observed by utilizing the proposed pulse-generator technique. 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A novel technique is used to generate a special clock-pulse wave (internally or externally) for flip-flop circuits. This technique shows better characteristics compared to existing techniques in terms of delay and power. The generated pulse is applied to different flip-flop topologies to show the efficacy of the proposed technique on power and speed. Simulation results show improvement in setup time compared to their counterparts. Furthermore, at least 20% improvement in power consumption is observed by utilizing the proposed pulse-generator technique. IBM 65nm Models are used for simulation using CADENCE and Synopsys tools.</description><subject>Clocks</subject><subject>Delay</subject><subject>Flip-flops</subject><subject>Power demand</subject><subject>Pulse generation</subject><subject>Topology</subject><subject>Transistors</subject><isbn>1467312614</isbn><isbn>9781467312615</isbn><isbn>1467312606</isbn><isbn>9781467312592</isbn><isbn>9781467312608</isbn><isbn>1467312592</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFj91KAzEUhCMiqG1fQG_yArvmJNmT5lKWVgsFL7TXJZuerJE1u-6P4Nu7YMGrYeZjBoaxOxA5gLAPu3JTvuZSgMxRo0KlLtgtaDQKJAq8_Degr9lqGD6EEHMTrcQbZrZN7LLQtB0_0RDrxKchppqn9psa3k3NQLymRL0bY5v4SP49xa-JluwquBmuzrpgh-3mrXzO9i9Pu_Jxn0UwxZihqzydirVUYKEw6LT0ldVqTi0qcmuSMgRnDUBAb6vCaK8rcGgMyaC9WrD7v91IRMeuj5-u_zmej6pffuBHOg</recordid><startdate>201212</startdate><enddate>201212</enddate><creator>Moradi, F.</creator><creator>Wisland, D.</creator><creator>Kargaard Madsen, Jens</creator><creator>Mahmoodi, H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201212</creationdate><title>Flip-flop design using novel pulse generation technique</title><author>Moradi, F. ; Wisland, D. ; Kargaard Madsen, Jens ; Mahmoodi, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-6abced5823191576a42cb943bce963ea8e22ffa9711f6c9b574c4b1a677e2f4c3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Clocks</topic><topic>Delay</topic><topic>Flip-flops</topic><topic>Power demand</topic><topic>Pulse generation</topic><topic>Topology</topic><topic>Transistors</topic><toplevel>online_resources</toplevel><creatorcontrib>Moradi, F.</creatorcontrib><creatorcontrib>Wisland, D.</creatorcontrib><creatorcontrib>Kargaard Madsen, Jens</creatorcontrib><creatorcontrib>Mahmoodi, H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Moradi, F.</au><au>Wisland, D.</au><au>Kargaard Madsen, Jens</au><au>Mahmoodi, H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Flip-flop design using novel pulse generation technique</atitle><btitle>2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)</btitle><stitle>ICECS</stitle><date>2012-12</date><risdate>2012</risdate><spage>685</spage><epage>688</epage><pages>685-688</pages><isbn>1467312614</isbn><isbn>9781467312615</isbn><eisbn>1467312606</eisbn><eisbn>9781467312592</eisbn><eisbn>9781467312608</eisbn><eisbn>1467312592</eisbn><abstract>In this paper, new flip-flop topologies for low power and high-speed digital designs are presented. A novel technique is used to generate a special clock-pulse wave (internally or externally) for flip-flop circuits. This technique shows better characteristics compared to existing techniques in terms of delay and power. The generated pulse is applied to different flip-flop topologies to show the efficacy of the proposed technique on power and speed. Simulation results show improvement in setup time compared to their counterparts. Furthermore, at least 20% improvement in power consumption is observed by utilizing the proposed pulse-generator technique. IBM 65nm Models are used for simulation using CADENCE and Synopsys tools.</abstract><pub>IEEE</pub><doi>10.1109/ICECS.2012.6463633</doi><tpages>4</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks Delay Flip-flops Power demand Pulse generation Topology Transistors |
| title | Flip-flop design using novel pulse generation technique |
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