Improving the accuracy and performance of memory communication through renaming

As processors continue to exploit more instruction-level parallelism, a greater demand is placed on reducing the effects of memory access latency. In this paper, we introduce a novel modification of the processor pipeline called memory renaming. Memory renaming applies register access techniques to...

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Bibliographische Detailangaben

Hauptverfasser:	Tyson, G.S., Austin, T.M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks Delay effects Dynamic scheduling Memory management Microcomputers Microprocessors Out of order Pipelines Random access memory Registers
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