Graded-channel MOSFET (GCMOSFET) for high performance, low voltage DSP applications
Graded-Channel MOS (GCMOS) VLSI technology has been developed to meet the growing demand for low power and high performance applications. In this paper, it will be shown that, compared to conventional complementary metal-oxide-semiconductor (CMOS), the GCMOS device offers the advantage of significan...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 1997-12, Vol.5 (4), p.352-359 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Jun Ma Han-Bin Liang Pryor, R.A. Cheng, S. Kaneshiro, M.H. Kyono, C.S. Papworth, K. |
| description | Graded-Channel MOS (GCMOS) VLSI technology has been developed to meet the growing demand for low power and high performance applications. In this paper, it will be shown that, compared to conventional complementary metal-oxide-semiconductor (CMOS), the GCMOS device offers the advantage of significantly higher drive current, capable of lower threshold voltage with improved punchthrough resistance, lower body effect and lower series resistance, thus making it most suitable for applications that require both high performance and low power consumption, such as digital signal processing (DSP). This is demonstrated, for the first time, by much improved low voltage circuit performance of a DSP logic circuit fabricated using a 0.5 /spl mu/m GCMOS process. At 1.8 V, a 30% speed improvement over CMOS is achieved, and the power-delay product is reduced by 25%. In addition, similar speed improvement is achieved in SRAM's with consistent performance improvement over a wide range of temperatures between -50 and 150/spl deg/C. |
| doi_str_mv | 10.1109/92.645061 |
| format | Article |
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In this paper, it will be shown that, compared to conventional complementary metal-oxide-semiconductor (CMOS), the GCMOS device offers the advantage of significantly higher drive current, capable of lower threshold voltage with improved punchthrough resistance, lower body effect and lower series resistance, thus making it most suitable for applications that require both high performance and low power consumption, such as digital signal processing (DSP). This is demonstrated, for the first time, by much improved low voltage circuit performance of a DSP logic circuit fabricated using a 0.5 /spl mu/m GCMOS process. At 1.8 V, a 30% speed improvement over CMOS is achieved, and the power-delay product is reduced by 25%. In addition, similar speed improvement is achieved in SRAM's with consistent performance improvement over a wide range of temperatures between -50 and 150/spl deg/C.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/92.645061</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>Piscataway, NJ: IEEE</publisher><subject>Applied sciences ; Circuit optimization ; CMOS process ; CMOS technology ; Digital signal processing ; Electronics ; Energy consumption ; Exact sciences and technology ; Immune system ; Low voltage ; MOSFET circuits ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Threshold voltage ; Transistors ; Very large scale integration</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 1997-12, Vol.5 (4), p.352-359</ispartof><rights>1998 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c434t-97dba7f05ea7b51f1803a2ac5a053123572628be652135c92b1183cb72a132203</citedby><cites>FETCH-LOGICAL-c434t-97dba7f05ea7b51f1803a2ac5a053123572628be652135c92b1183cb72a132203</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/645061$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,776,780,785,786,792,23909,23910,25118,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/645061$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=2130289$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Jun Ma</creatorcontrib><creatorcontrib>Han-Bin Liang</creatorcontrib><creatorcontrib>Pryor, R.A.</creatorcontrib><creatorcontrib>Cheng, S.</creatorcontrib><creatorcontrib>Kaneshiro, M.H.</creatorcontrib><creatorcontrib>Kyono, C.S.</creatorcontrib><creatorcontrib>Papworth, K.</creatorcontrib><title>Graded-channel MOSFET (GCMOSFET) for high performance, low voltage DSP applications</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>Graded-Channel MOS (GCMOS) VLSI technology has been developed to meet the growing demand for low power and high performance applications. In this paper, it will be shown that, compared to conventional complementary metal-oxide-semiconductor (CMOS), the GCMOS device offers the advantage of significantly higher drive current, capable of lower threshold voltage with improved punchthrough resistance, lower body effect and lower series resistance, thus making it most suitable for applications that require both high performance and low power consumption, such as digital signal processing (DSP). This is demonstrated, for the first time, by much improved low voltage circuit performance of a DSP logic circuit fabricated using a 0.5 /spl mu/m GCMOS process. At 1.8 V, a 30% speed improvement over CMOS is achieved, and the power-delay product is reduced by 25%. In addition, similar speed improvement is achieved in SRAM's with consistent performance improvement over a wide range of temperatures between -50 and 150/spl deg/C.</description><subject>Applied sciences</subject><subject>Circuit optimization</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Digital signal processing</subject><subject>Electronics</subject><subject>Energy consumption</subject><subject>Exact sciences and technology</subject><subject>Immune system</subject><subject>Low voltage</subject><subject>MOSFET circuits</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Threshold voltage</subject><subject>Transistors</subject><subject>Very large scale integration</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1997</creationdate><recordtype>article</recordtype><recordid>eNqNkctLw0AQxoMoWKsHr572IGLB1H1kX0epWoVKheo5TLabNrJN4m6r-N-7JaVXnct8ML_5mEeSnBM8JATrW02HIuNYkIOkRziXqY5xGDUWLFWU4OPkJIQPjEmWadxLZmMPcztPzRLq2jr0Mp09Pryh6_GoUwNUNh4tq8UStdZHvYLa2Bvkmm_01bg1LCy6n70iaFtXGVhXTR1Ok6MSXLBnu9xP3qPT6CmdTMfPo7tJajKWrVMt5wXIEnMLsuCkJAozoGA4YM4IZVxSQVVhBaeEcaNpQYhippAUCKMUs35y1fm2vvnc2LDOV1Uw1jmobbMJOVUaU03kP0BGhdLqb1BwxYXcgoMONL4Jwdsyb321Av-TE5xvH5FrmnePiOzlzhSCAVf6eMEq7BvicjhOGrGLDqustfvqzuMXWqqLtw</recordid><startdate>19971201</startdate><enddate>19971201</enddate><creator>Jun Ma</creator><creator>Han-Bin Liang</creator><creator>Pryor, R.A.</creator><creator>Cheng, S.</creator><creator>Kaneshiro, M.H.</creator><creator>Kyono, C.S.</creator><creator>Papworth, K.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19971201</creationdate><title>Graded-channel MOSFET (GCMOSFET) for high performance, low voltage DSP applications</title><author>Jun Ma ; Han-Bin Liang ; Pryor, R.A. ; Cheng, S. ; Kaneshiro, M.H. ; Kyono, C.S. ; Papworth, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c434t-97dba7f05ea7b51f1803a2ac5a053123572628be652135c92b1183cb72a132203</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1997</creationdate><topic>Applied sciences</topic><topic>Circuit optimization</topic><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Digital signal processing</topic><topic>Electronics</topic><topic>Energy consumption</topic><topic>Exact sciences and technology</topic><topic>Immune system</topic><topic>Low voltage</topic><topic>MOSFET circuits</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Threshold voltage</topic><topic>Transistors</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Jun Ma</creatorcontrib><creatorcontrib>Han-Bin Liang</creatorcontrib><creatorcontrib>Pryor, R.A.</creatorcontrib><creatorcontrib>Cheng, S.</creatorcontrib><creatorcontrib>Kaneshiro, M.H.</creatorcontrib><creatorcontrib>Kyono, C.S.</creatorcontrib><creatorcontrib>Papworth, K.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jun Ma</au><au>Han-Bin Liang</au><au>Pryor, R.A.</au><au>Cheng, S.</au><au>Kaneshiro, M.H.</au><au>Kyono, C.S.</au><au>Papworth, K.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Graded-channel MOSFET (GCMOSFET) for high performance, low voltage DSP applications</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>1997-12-01</date><risdate>1997</risdate><volume>5</volume><issue>4</issue><spage>352</spage><epage>359</epage><pages>352-359</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>Graded-Channel MOS (GCMOS) VLSI technology has been developed to meet the growing demand for low power and high performance applications. In this paper, it will be shown that, compared to conventional complementary metal-oxide-semiconductor (CMOS), the GCMOS device offers the advantage of significantly higher drive current, capable of lower threshold voltage with improved punchthrough resistance, lower body effect and lower series resistance, thus making it most suitable for applications that require both high performance and low power consumption, such as digital signal processing (DSP). This is demonstrated, for the first time, by much improved low voltage circuit performance of a DSP logic circuit fabricated using a 0.5 /spl mu/m GCMOS process. At 1.8 V, a 30% speed improvement over CMOS is achieved, and the power-delay product is reduced by 25%. In addition, similar speed improvement is achieved in SRAM's with consistent performance improvement over a wide range of temperatures between -50 and 150/spl deg/C.</abstract><cop>Piscataway, NJ</cop><pub>IEEE</pub><doi>10.1109/92.645061</doi><tpages>8</tpages></addata></record> |
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| identifier | ISSN: 1063-8210 |
| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 1997-12, Vol.5 (4), p.352-359 |
| issn | 1063-8210 1557-9999 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Circuit optimization CMOS process CMOS technology Digital signal processing Electronics Energy consumption Exact sciences and technology Immune system Low voltage MOSFET circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Threshold voltage Transistors Very large scale integration |
| title | Graded-channel MOSFET (GCMOSFET) for high performance, low voltage DSP applications |
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