A region-based theory for state assignment in speed-independent circuits
State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair of different states in a specification has the same binary encoding. A standard...
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Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 1997-08, Vol.16 (8), p.793-812 |
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creator | Cortadella, J. Kishinevsky, M. Kondratyev, A. Lavagno, L. Yakovlev, A. |
description | State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair of different states in a specification has the same binary encoding. A standard way to approach state coding conflicts is to insert new state signals into the original specification in such a way that the original behavior remains intact. This paper proposes a method which improves over existing approaches by coupling generality, optimality, and efficiency. The method is based on the use of a class of "ground objects", called regions, that play the role of a bridge between state-based specifications (transition systems, TS's) and event-based specifications (signal transition graphs, STG's), We need to deal with both types of specification because designers usually prefer a timing diagram-like notation, such as STG, while optimization and cost analysis work better at the state level. A region in a transition system is a set of states that corresponds to a place in an STG (or the underlying Petri net). Regions are tightly connected with a set of properties that are to be preserved across the state encoding process, namely, 1) trace equivalence between the original and the encoded specification, and 2) implementability as a speed-independent circuit. We will build on a theoretical body of work that has shown the significance of regions for such property-preserving transformations, and describe a set of algorithms aimed at efficiently solving the encoding problem. The algorithms have been implemented in a software tool called petrify. Unlike many existing tools, petrify represents the encoded specification as an STG. This significantly improves the readability of the result (compared to a state-based description in which concurrency is represented implicitly by interleaving), and allows the designer to be more closely involved in the synthesis process. The efficiency of the method is demonstrated on a number of "difficult" examples. |
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A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair of different states in a specification has the same binary encoding. A standard way to approach state coding conflicts is to insert new state signals into the original specification in such a way that the original behavior remains intact. This paper proposes a method which improves over existing approaches by coupling generality, optimality, and efficiency. The method is based on the use of a class of "ground objects", called regions, that play the role of a bridge between state-based specifications (transition systems, TS's) and event-based specifications (signal transition graphs, STG's), We need to deal with both types of specification because designers usually prefer a timing diagram-like notation, such as STG, while optimization and cost analysis work better at the state level. A region in a transition system is a set of states that corresponds to a place in an STG (or the underlying Petri net). Regions are tightly connected with a set of properties that are to be preserved across the state encoding process, namely, 1) trace equivalence between the original and the encoded specification, and 2) implementability as a speed-independent circuit. We will build on a theoretical body of work that has shown the significance of regions for such property-preserving transformations, and describe a set of algorithms aimed at efficiently solving the encoding problem. The algorithms have been implemented in a software tool called petrify. Unlike many existing tools, petrify represents the encoded specification as an STG. This significantly improves the readability of the result (compared to a state-based description in which concurrency is represented implicitly by interleaving), and allows the designer to be more closely involved in the synthesis process. The efficiency of the method is demonstrated on a number of "difficult" examples.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/43.644602</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Asynchronous circuits ; Bridge circuits ; Circuit synthesis ; Circuits asíncrons ; Cost function ; Design optimization ; Design. Technologies. Operation analysis. Testing ; Electronics ; Encoding ; Enginyeria electrònica ; Estructura lògica ; Exact sciences and technology ; Integrated circuits ; Logic CAD ; Logic design ; Microelectrònica ; Petri nets ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Signal analysis ; Signal design ; Signal flow graphs ; Signal synthesis ; State assignment ; Timing ; Àrees temàtiques de la UPC</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 1997-08, Vol.16 (8), p.793-812</ispartof><rights>1998 INIST-CNRS</rights><rights>info:eu-repo/semantics/openAccess</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c317t-95520144a4ba91f6276214ed16b088597f7212652d832879d9ab97b1e14a40753</citedby><cites>FETCH-LOGICAL-c317t-95520144a4ba91f6276214ed16b088597f7212652d832879d9ab97b1e14a40753</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/644602$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>230,314,776,780,792,881,26953,27903,27904,54736</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/644602$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=2136714$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Cortadella, J.</creatorcontrib><creatorcontrib>Kishinevsky, M.</creatorcontrib><creatorcontrib>Kondratyev, A.</creatorcontrib><creatorcontrib>Lavagno, L.</creatorcontrib><creatorcontrib>Yakovlev, A.</creatorcontrib><title>A region-based theory for state assignment in speed-independent circuits</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description>State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair of different states in a specification has the same binary encoding. A standard way to approach state coding conflicts is to insert new state signals into the original specification in such a way that the original behavior remains intact. This paper proposes a method which improves over existing approaches by coupling generality, optimality, and efficiency. The method is based on the use of a class of "ground objects", called regions, that play the role of a bridge between state-based specifications (transition systems, TS's) and event-based specifications (signal transition graphs, STG's), We need to deal with both types of specification because designers usually prefer a timing diagram-like notation, such as STG, while optimization and cost analysis work better at the state level. A region in a transition system is a set of states that corresponds to a place in an STG (or the underlying Petri net). Regions are tightly connected with a set of properties that are to be preserved across the state encoding process, namely, 1) trace equivalence between the original and the encoded specification, and 2) implementability as a speed-independent circuit. We will build on a theoretical body of work that has shown the significance of regions for such property-preserving transformations, and describe a set of algorithms aimed at efficiently solving the encoding problem. The algorithms have been implemented in a software tool called petrify. Unlike many existing tools, petrify represents the encoded specification as an STG. This significantly improves the readability of the result (compared to a state-based description in which concurrency is represented implicitly by interleaving), and allows the designer to be more closely involved in the synthesis process. The efficiency of the method is demonstrated on a number of "difficult" examples.</description><subject>Applied sciences</subject><subject>Asynchronous circuits</subject><subject>Bridge circuits</subject><subject>Circuit synthesis</subject><subject>Circuits asíncrons</subject><subject>Cost function</subject><subject>Design optimization</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Encoding</subject><subject>Enginyeria electrònica</subject><subject>Estructura lògica</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Logic CAD</subject><subject>Logic design</subject><subject>Microelectrònica</subject><subject>Petri nets</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Signal analysis</subject><subject>Signal design</subject><subject>Signal flow graphs</subject><subject>Signal synthesis</subject><subject>State assignment</subject><subject>Timing</subject><subject>Àrees temàtiques de la UPC</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1997</creationdate><recordtype>article</recordtype><sourceid>XX2</sourceid><recordid>eNpFkD1PwzAQhi0EEqUwsDJlYGFI8fkjjseqAopUiQVmy3EuxahNItsd-u8xSlWGu9Pdvc970hFyD3QBQPWz4ItKiIqyCzIDzVUpQMIlmVGm6pJSRa_JTYw_lIKQTM_IelkE3PqhLxsbsS3SNw7hWHRDKGKyCQsbo9_2e-xT4fsijoht6fsWR8wpD50P7uBTvCVXnd1FvDvVOfl6fflcrcvNx9v7arkpHQeVSi0ly7eFFY3V0FVMVQwEtlA1tK6lVp1iwCrJ2pqzWulW20arBhAyQpXkcwKTr4sHZwI6DM4mM1j_3_wFo4oZzpVWPDNPJyYMMQbszBj83oajAWr-3mYEN9PbsvZx0o42Orvrgu2dj2eAAa8UiCx7mGQeEc_bk8cvpadyaw</recordid><startdate>19970801</startdate><enddate>19970801</enddate><creator>Cortadella, J.</creator><creator>Kishinevsky, M.</creator><creator>Kondratyev, A.</creator><creator>Lavagno, L.</creator><creator>Yakovlev, A.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>XX2</scope></search><sort><creationdate>19970801</creationdate><title>A region-based theory for state assignment in speed-independent circuits</title><author>Cortadella, J. ; Kishinevsky, M. ; Kondratyev, A. ; Lavagno, L. ; Yakovlev, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c317t-95520144a4ba91f6276214ed16b088597f7212652d832879d9ab97b1e14a40753</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1997</creationdate><topic>Applied sciences</topic><topic>Asynchronous circuits</topic><topic>Bridge circuits</topic><topic>Circuit synthesis</topic><topic>Circuits asíncrons</topic><topic>Cost function</topic><topic>Design optimization</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Encoding</topic><topic>Enginyeria electrònica</topic><topic>Estructura lògica</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Logic CAD</topic><topic>Logic design</topic><topic>Microelectrònica</topic><topic>Petri nets</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Signal analysis</topic><topic>Signal design</topic><topic>Signal flow graphs</topic><topic>Signal synthesis</topic><topic>State assignment</topic><topic>Timing</topic><topic>Àrees temàtiques de la UPC</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Cortadella, J.</creatorcontrib><creatorcontrib>Kishinevsky, M.</creatorcontrib><creatorcontrib>Kondratyev, A.</creatorcontrib><creatorcontrib>Lavagno, L.</creatorcontrib><creatorcontrib>Yakovlev, A.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Recercat</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Cortadella, J.</au><au>Kishinevsky, M.</au><au>Kondratyev, A.</au><au>Lavagno, L.</au><au>Yakovlev, A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A region-based theory for state assignment in speed-independent circuits</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>1997-08-01</date><risdate>1997</risdate><volume>16</volume><issue>8</issue><spage>793</spage><epage>812</epage><pages>793-812</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair of different states in a specification has the same binary encoding. A standard way to approach state coding conflicts is to insert new state signals into the original specification in such a way that the original behavior remains intact. This paper proposes a method which improves over existing approaches by coupling generality, optimality, and efficiency. The method is based on the use of a class of "ground objects", called regions, that play the role of a bridge between state-based specifications (transition systems, TS's) and event-based specifications (signal transition graphs, STG's), We need to deal with both types of specification because designers usually prefer a timing diagram-like notation, such as STG, while optimization and cost analysis work better at the state level. A region in a transition system is a set of states that corresponds to a place in an STG (or the underlying Petri net). Regions are tightly connected with a set of properties that are to be preserved across the state encoding process, namely, 1) trace equivalence between the original and the encoded specification, and 2) implementability as a speed-independent circuit. We will build on a theoretical body of work that has shown the significance of regions for such property-preserving transformations, and describe a set of algorithms aimed at efficiently solving the encoding problem. The algorithms have been implemented in a software tool called petrify. Unlike many existing tools, petrify represents the encoded specification as an STG. This significantly improves the readability of the result (compared to a state-based description in which concurrency is represented implicitly by interleaving), and allows the designer to be more closely involved in the synthesis process. The efficiency of the method is demonstrated on a number of "difficult" examples.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/43.644602</doi><tpages>20</tpages><oa>free_for_read</oa></addata></record> |
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subjects | Applied sciences Asynchronous circuits Bridge circuits Circuit synthesis Circuits asíncrons Cost function Design optimization Design. Technologies. Operation analysis. Testing Electronics Encoding Enginyeria electrònica Estructura lògica Exact sciences and technology Integrated circuits Logic CAD Logic design Microelectrònica Petri nets Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal analysis Signal design Signal flow graphs Signal synthesis State assignment Timing Àrees temàtiques de la UPC |
title | A region-based theory for state assignment in speed-independent circuits |
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