Buffer size minimization method considering mix-clock domains and discontinuous data access
We propose a method to minimize the buffer size for applications requiring internal multiple clock frequencies and discontinuous data access. The buffer needs not only to handle synchronization between different frequencies, but also to deal with non-first-in-first-out (FIFO) type data access patter...
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creator | Lih-Yih Chiou Liang-Ying Lu Bo-Chi Lin Su, Alan P. |
description | We propose a method to minimize the buffer size for applications requiring internal multiple clock frequencies and discontinuous data access. The buffer needs not only to handle synchronization between different frequencies, but also to deal with non-first-in-first-out (FIFO) type data access patterns. The proposed method transforms the minimization problem into a graph representation and adopts vertex coloring to minimize the buffer size while meeting the throughput constraints. The experimental results show that the maximum area of the buffer designed by the proposed method is 66.28% smaller than that of a comparable buffer. |
doi_str_mv | 10.1109/APCCAS.2012.6419051 |
format | Conference Proceeding |
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The experimental results show that the maximum area of the buffer designed by the proposed method is 66.28% smaller than that of a comparable buffer.</description><identifier>EISBN: 1457717298</identifier><identifier>EISBN: 9781457717291</identifier><identifier>EISBN: 145771728X</identifier><identifier>EISBN: 9781457717284</identifier><identifier>DOI: 10.1109/APCCAS.2012.6419051</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computer architecture ; Minimization methods ; Power demand ; Scheduling ; Synchronization ; Throughput</subject><ispartof>2012 IEEE Asia Pacific Conference on Circuits and Systems, 2012, p.380-383</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6419051$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27904,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6419051$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Lih-Yih Chiou</creatorcontrib><creatorcontrib>Liang-Ying Lu</creatorcontrib><creatorcontrib>Bo-Chi Lin</creatorcontrib><creatorcontrib>Su, Alan P.</creatorcontrib><title>Buffer size minimization method considering mix-clock domains and discontinuous data access</title><title>2012 IEEE Asia Pacific Conference on Circuits and Systems</title><addtitle>APCCAS</addtitle><description>We propose a method to minimize the buffer size for applications requiring internal multiple clock frequencies and discontinuous data access. The buffer needs not only to handle synchronization between different frequencies, but also to deal with non-first-in-first-out (FIFO) type data access patterns. The proposed method transforms the minimization problem into a graph representation and adopts vertex coloring to minimize the buffer size while meeting the throughput constraints. The experimental results show that the maximum area of the buffer designed by the proposed method is 66.28% smaller than that of a comparable buffer.</description><subject>Computer architecture</subject><subject>Minimization methods</subject><subject>Power demand</subject><subject>Scheduling</subject><subject>Synchronization</subject><subject>Throughput</subject><isbn>1457717298</isbn><isbn>9781457717291</isbn><isbn>145771728X</isbn><isbn>9781457717284</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tKxDAYRuNCUMd5gtnkBVrz59osa_EGAwrqysWQJqn-Ok2laUHn6S04q7P4Dh8cQjbASgBmr-qnpqmfS86Al1qCZQpOyAVIZQwYbqszss75kzEGRmsB-py8Xc9dF0ea8RBpjwl7PLgJh0T7OH0MgfohZQxxxPS-7D-F3w_-i4ahd5gydSnQgHmRJkzzMGca3OSo8z7mfElOO7fPcX3kirze3rw098X28e6hqbcFglFT0fEQVHBaM8Er7oMwHkIVZZDMViBtay0XrXSaq25xW6akabnSlYggveRiRTb_vxhj3H2P2Lvxd3fsF3947lJl</recordid><startdate>201212</startdate><enddate>201212</enddate><creator>Lih-Yih Chiou</creator><creator>Liang-Ying Lu</creator><creator>Bo-Chi Lin</creator><creator>Su, Alan P.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201212</creationdate><title>Buffer size minimization method considering mix-clock domains and discontinuous data access</title><author>Lih-Yih Chiou ; Liang-Ying Lu ; Bo-Chi Lin ; Su, Alan P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-f2dd5da6603282cd37c1d8e4d4098149b9923b4a625ff2db0547b25683e14c423</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Computer architecture</topic><topic>Minimization methods</topic><topic>Power demand</topic><topic>Scheduling</topic><topic>Synchronization</topic><topic>Throughput</topic><toplevel>online_resources</toplevel><creatorcontrib>Lih-Yih Chiou</creatorcontrib><creatorcontrib>Liang-Ying Lu</creatorcontrib><creatorcontrib>Bo-Chi Lin</creatorcontrib><creatorcontrib>Su, Alan P.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lih-Yih Chiou</au><au>Liang-Ying Lu</au><au>Bo-Chi Lin</au><au>Su, Alan P.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Buffer size minimization method considering mix-clock domains and discontinuous data access</atitle><btitle>2012 IEEE Asia Pacific Conference on Circuits and Systems</btitle><stitle>APCCAS</stitle><date>2012-12</date><risdate>2012</risdate><spage>380</spage><epage>383</epage><pages>380-383</pages><eisbn>1457717298</eisbn><eisbn>9781457717291</eisbn><eisbn>145771728X</eisbn><eisbn>9781457717284</eisbn><abstract>We propose a method to minimize the buffer size for applications requiring internal multiple clock frequencies and discontinuous data access. The buffer needs not only to handle synchronization between different frequencies, but also to deal with non-first-in-first-out (FIFO) type data access patterns. The proposed method transforms the minimization problem into a graph representation and adopts vertex coloring to minimize the buffer size while meeting the throughput constraints. The experimental results show that the maximum area of the buffer designed by the proposed method is 66.28% smaller than that of a comparable buffer.</abstract><pub>IEEE</pub><doi>10.1109/APCCAS.2012.6419051</doi><tpages>4</tpages></addata></record> |
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subjects | Computer architecture Minimization methods Power demand Scheduling Synchronization Throughput |
title | Buffer size minimization method considering mix-clock domains and discontinuous data access |
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