An efficient asymmetric distributed lock for embedded multiprocessor systems

Efficient synchronization is a key concern in an embedded many-core system-on-chip (SoC). The use of atomic read-modify-write instructions combined with cache coherency as synchronization primitive is not always an option for shared-memory SoCs due to the lack of suitable IP. Furthermore, there are...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Rutgers, J. H., Bekooij, M. J. G., Smit, G. J. M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Bandwidth Hardware SDRAM Servers Synchronization System-on-a-chip Tiles
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