Just-in-Time Verification in ADL-based processor design

Just-in-Time Verification in ADL-based processor design

A novel verification methodology, combining the two new techniques of Live Verification and Processor State Transfer, is introduced to Architecture Description Language (ADL) based processor design. The proposed Just-in-Time Verification significantly accelerates the simulation-based equivalence che...

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Hauptverfasser: Auras, D., Minwegen, A., Deidersen, U., Schurmans, S., Ascheid, G., Leupers, R.
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Sprache:eng
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Computer architecture
Debugging
Hardware design languages
History
Mathematical model
Pipelines
Registers
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creator Auras, D.
Minwegen, A.
Deidersen, U.
Schurmans, S.
Ascheid, G.
Leupers, R.
description A novel verification methodology, combining the two new techniques of Live Verification and Processor State Transfer, is introduced to Architecture Description Language (ADL) based processor design. The proposed Just-in-Time Verification significantly accelerates the simulation-based equivalence check of the register-transfer and instruction-set level models, generated from the ADL-based specification. This is accomplished by omitting redundant simulation steps occurring in the conventional architecture debug cycle. The potential speedup is demonstrated with a case study, achieving an acceleration of the debug cycle by 660x.
doi_str_mv 10.1109/SAMOS.2012.6404151
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subjects Computer architecture
Debugging
Hardware design languages
History
Mathematical model
Pipelines
Registers
title Just-in-Time Verification in ADL-based processor design
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