A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOS

In this paper, a design of an asynchronous differential SAR ADC is presented. The ADC uses a dynamic two-stage comparator with a current source to improve linearity, a digital SAR control logic, bootstrapped sampling switches with body effect reduction, and a charge redistribution differential DAC w...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Tuan-Vu Cao, Aunet, S., Ytterdal, T.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Capacitors CMOS integrated circuits Logic gates Noise Power demand Switches Transistors
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