Test challenges in designing complex 3D chips: What in on the horizon for EDA industry?: Designer track

Summary form only given. Recent advances in semiconductor process technology especially interconnects using Through-Silicon Vias (TSVs) enable heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and then stacked together to form a system. Compared...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Goel, S. K.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	3D Stacked ICs Companies Conferences Design-for-Test Industries Manufacturing Silicon Silicon Interposer Stacking Test Architecture and Wrappers Testing
Online-Zugang:	Volltext bestellen
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