Efficient verification of out-of-order behaviors with relaxed scoreboards

Efficient verification of out-of-order behaviors with relaxed scoreboards

Microarchitectures often relax order constraints to meet performance requirements. However, the design of a module handling out-of-order behaviors is error prone, since order relaxation asks for sophisticated control. Besides, its functional verification is challenging, because the module does not p...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Freitas, L. S., Andrade, G. A. G., dos Santos, L. C. V.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bipartite graph
Computer science
Educational institutions
Heuristic algorithms
Out of order
Protocols
Runtime
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 511
container_issue
container_start_page 510
container_title
container_volume
creator Freitas, L. S.
Andrade, G. A. G.
dos Santos, L. C. V.
description Microarchitectures often relax order constraints to meet performance requirements. However, the design of a module handling out-of-order behaviors is error prone, since order relaxation asks for sophisticated control. Besides, its functional verification is challenging, because the module does not preserve at its output the order corresponding to its input data, violating a basic assumption of conventional scoreboards. This paper discusses the verification guarantees of three classes of dynamic checkers and experimentally compares their effectiveness and effort. Results show that a well-designed relaxed scoreboard can achieve the same effectiveness as a complete post-mortem checker with an effort similar to a conventional scoreboard's.
doi_str_mv 10.1109/ICCD.2012.6378698
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6378698</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6378698</ieee_id><sourcerecordid>6378698</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-f209cf0a4ed38ebfbe7370eaf0472a0c219da610456f5a279d342553ea46899f3</originalsourceid><addsrcrecordid>eNo1kMtKAzEYRuMNnNY-gLjJC2T8c58sZaw6UHCj65KZ_KGR2khmrPr2Fqyr78CBs_gIueZQcw7utmvb-1oAF7WRtjGuOSELZxuujJUSNMhTUgltDTPOmTMy-xdcn5OKg5HMKFCXZDaObwDQSG4r0i1jTEPC3UT3WNKB_ZTyjuZI8-fEcmS5BCy0x43fp1xG-pWmDS249d8Y6Djkgn32JYxX5CL67YiL487J68PypX1iq-fHrr1bscStnlgU4IYIXmGQDfaxRystoI-grPAwCO6CNxyUNlF7YV2QSmgt0SvTOBflnNz8dRMirj9KevflZ328RP4C8lhRUQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Efficient verification of out-of-order behaviors with relaxed scoreboards</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Freitas, L. S. ; Andrade, G. A. G. ; dos Santos, L. C. V.</creator><creatorcontrib>Freitas, L. S. ; Andrade, G. A. G. ; dos Santos, L. C. V.</creatorcontrib><description>Microarchitectures often relax order constraints to meet performance requirements. However, the design of a module handling out-of-order behaviors is error prone, since order relaxation asks for sophisticated control. Besides, its functional verification is challenging, because the module does not preserve at its output the order corresponding to its input data, violating a basic assumption of conventional scoreboards. This paper discusses the verification guarantees of three classes of dynamic checkers and experimentally compares their effectiveness and effort. Results show that a well-designed relaxed scoreboard can achieve the same effectiveness as a complete post-mortem checker with an effort similar to a conventional scoreboard's.</description><identifier>ISSN: 1063-6404</identifier><identifier>ISBN: 1467330515</identifier><identifier>ISBN: 9781467330510</identifier><identifier>EISSN: 2576-6996</identifier><identifier>EISBN: 9781467330503</identifier><identifier>EISBN: 9781467330527</identifier><identifier>EISBN: 1467330523</identifier><identifier>EISBN: 1467330507</identifier><identifier>DOI: 10.1109/ICCD.2012.6378698</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bipartite graph ; Computer science ; Educational institutions ; Heuristic algorithms ; Out of order ; Protocols ; Runtime</subject><ispartof>2012 IEEE 30th International Conference on Computer Design (ICCD), 2012, p.510-511</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6378698$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6378698$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Freitas, L. S.</creatorcontrib><creatorcontrib>Andrade, G. A. G.</creatorcontrib><creatorcontrib>dos Santos, L. C. V.</creatorcontrib><title>Efficient verification of out-of-order behaviors with relaxed scoreboards</title><title>2012 IEEE 30th International Conference on Computer Design (ICCD)</title><addtitle>ICCD</addtitle><description>Microarchitectures often relax order constraints to meet performance requirements. However, the design of a module handling out-of-order behaviors is error prone, since order relaxation asks for sophisticated control. Besides, its functional verification is challenging, because the module does not preserve at its output the order corresponding to its input data, violating a basic assumption of conventional scoreboards. This paper discusses the verification guarantees of three classes of dynamic checkers and experimentally compares their effectiveness and effort. Results show that a well-designed relaxed scoreboard can achieve the same effectiveness as a complete post-mortem checker with an effort similar to a conventional scoreboard's.</description><subject>Bipartite graph</subject><subject>Computer science</subject><subject>Educational institutions</subject><subject>Heuristic algorithms</subject><subject>Out of order</subject><subject>Protocols</subject><subject>Runtime</subject><issn>1063-6404</issn><issn>2576-6996</issn><isbn>1467330515</isbn><isbn>9781467330510</isbn><isbn>9781467330503</isbn><isbn>9781467330527</isbn><isbn>1467330523</isbn><isbn>1467330507</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kMtKAzEYRuMNnNY-gLjJC2T8c58sZaw6UHCj65KZ_KGR2khmrPr2Fqyr78CBs_gIueZQcw7utmvb-1oAF7WRtjGuOSELZxuujJUSNMhTUgltDTPOmTMy-xdcn5OKg5HMKFCXZDaObwDQSG4r0i1jTEPC3UT3WNKB_ZTyjuZI8-fEcmS5BCy0x43fp1xG-pWmDS249d8Y6Djkgn32JYxX5CL67YiL487J68PypX1iq-fHrr1bscStnlgU4IYIXmGQDfaxRystoI-grPAwCO6CNxyUNlF7YV2QSmgt0SvTOBflnNz8dRMirj9KevflZ328RP4C8lhRUQ</recordid><startdate>201209</startdate><enddate>201209</enddate><creator>Freitas, L. S.</creator><creator>Andrade, G. A. G.</creator><creator>dos Santos, L. C. V.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201209</creationdate><title>Efficient verification of out-of-order behaviors with relaxed scoreboards</title><author>Freitas, L. S. ; Andrade, G. A. G. ; dos Santos, L. C. V.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-f209cf0a4ed38ebfbe7370eaf0472a0c219da610456f5a279d342553ea46899f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Bipartite graph</topic><topic>Computer science</topic><topic>Educational institutions</topic><topic>Heuristic algorithms</topic><topic>Out of order</topic><topic>Protocols</topic><topic>Runtime</topic><toplevel>online_resources</toplevel><creatorcontrib>Freitas, L. S.</creatorcontrib><creatorcontrib>Andrade, G. A. G.</creatorcontrib><creatorcontrib>dos Santos, L. C. V.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Freitas, L. S.</au><au>Andrade, G. A. G.</au><au>dos Santos, L. C. V.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Efficient verification of out-of-order behaviors with relaxed scoreboards</atitle><btitle>2012 IEEE 30th International Conference on Computer Design (ICCD)</btitle><stitle>ICCD</stitle><date>2012-09</date><risdate>2012</risdate><spage>510</spage><epage>511</epage><pages>510-511</pages><issn>1063-6404</issn><eissn>2576-6996</eissn><isbn>1467330515</isbn><isbn>9781467330510</isbn><eisbn>9781467330503</eisbn><eisbn>9781467330527</eisbn><eisbn>1467330523</eisbn><eisbn>1467330507</eisbn><abstract>Microarchitectures often relax order constraints to meet performance requirements. However, the design of a module handling out-of-order behaviors is error prone, since order relaxation asks for sophisticated control. Besides, its functional verification is challenging, because the module does not preserve at its output the order corresponding to its input data, violating a basic assumption of conventional scoreboards. This paper discusses the verification guarantees of three classes of dynamic checkers and experimentally compares their effectiveness and effort. Results show that a well-designed relaxed scoreboard can achieve the same effectiveness as a complete post-mortem checker with an effort similar to a conventional scoreboard's.</abstract><pub>IEEE</pub><doi>10.1109/ICCD.2012.6378698</doi><tpages>2</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 1063-6404
ispartof 2012 IEEE 30th International Conference on Computer Design (ICCD), 2012, p.510-511
issn 1063-6404
2576-6996
language eng
recordid cdi_ieee_primary_6378698
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Bipartite graph
Computer science
Educational institutions
Heuristic algorithms
Out of order
Protocols
Runtime
title Efficient verification of out-of-order behaviors with relaxed scoreboards
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T04%3A23%3A21IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Efficient%20verification%20of%20out-of-order%20behaviors%20with%20relaxed%20scoreboards&rft.btitle=2012%20IEEE%2030th%20International%20Conference%20on%20Computer%20Design%20(ICCD)&rft.au=Freitas,%20L.%20S.&rft.date=2012-09&rft.spage=510&rft.epage=511&rft.pages=510-511&rft.issn=1063-6404&rft.eissn=2576-6996&rft.isbn=1467330515&rft.isbn_list=9781467330510&rft_id=info:doi/10.1109/ICCD.2012.6378698&rft_dat=%3Cieee_6IE%3E6378698%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781467330503&rft.eisbn_list=9781467330527&rft.eisbn_list=1467330523&rft.eisbn_list=1467330507&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6378698&rfr_iscdi=true