Direct GPU/FPGA Communication via PCI Express

Parallel processing has hit mainstream computing in the form of CPUs, GPUs and FPGAs. While explorations proceed with all three platforms individually and with the CPU-GPU pair, little exploration has been performed with the synergy of GPU-FPGA. This is due in part to the cumbersome nature of commun...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Bittner, R., Ruf, E.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 139
container_issue
container_start_page 135
container_title
container_volume
creator Bittner, R.
Ruf, E.
description Parallel processing has hit mainstream computing in the form of CPUs, GPUs and FPGAs. While explorations proceed with all three platforms individually and with the CPU-GPU pair, little exploration has been performed with the synergy of GPU-FPGA. This is due in part to the cumbersome nature of communication between the two. This paper presents a mechanism for direct GPU-FPGA communication and characterizes its performance in a full hardware implementation.
doi_str_mv 10.1109/ICPPW.2012.20
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6337472</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6337472</ieee_id><sourcerecordid>6337472</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-8e4903cc80a6b08a6a25c421a4fa42d6e9c8ed26ed114c1b9a5a42ffaf6894083</originalsourceid><addsrcrecordid>eNotjM1qwzAQhNU_qEl97KkXv4CSXUmWtMfgJq4hUB8ScgyKLINKnQTbLe3b17QdmPlgBoaxR4Q5ItCiKup6PxeAYoorlpKxYDTlyky-ZomQUvBcE9z8bqi0kSIHMrcsASTgktDes3QY3mCSFSgtJow_xz74MSvr3WJdl8usOHfdxyl6N8bzKfuMLquLKlt9XfowDA_srnXvQ0j_OWPb9WpbvPDNa1kVyw2PBCO3QRFI7y04fQTrtBO5VwKdap0SjQ7kbWiEDg2i8ngkl09927pWW1Jg5Yw9_d3GEMLh0sfO9d8HLaVRRsgfTC9Fmw</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Direct GPU/FPGA Communication via PCI Express</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Bittner, R. ; Ruf, E.</creator><creatorcontrib>Bittner, R. ; Ruf, E.</creatorcontrib><description>Parallel processing has hit mainstream computing in the form of CPUs, GPUs and FPGAs. While explorations proceed with all three platforms individually and with the CPU-GPU pair, little exploration has been performed with the synergy of GPU-FPGA. This is due in part to the cumbersome nature of communication between the two. This paper presents a mechanism for direct GPU-FPGA communication and characterizes its performance in a full hardware implementation.</description><identifier>ISSN: 0190-3918</identifier><identifier>ISBN: 9781467325097</identifier><identifier>ISBN: 1467325090</identifier><identifier>EISSN: 2332-5690</identifier><identifier>EISBN: 9780769547954</identifier><identifier>EISBN: 0769547958</identifier><identifier>DOI: 10.1109/ICPPW.2012.20</identifier><identifier>CODEN: IEEPAD</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bandwidth ; CUDA ; Field programmable gate arrays ; FPGA ; GPU ; Graphics processing unit ; Hardware ; Memory management ; nVidia ; Operating systems ; PCI Express ; PCIe ; Switches ; Verilog ; Windows ; Xilinx</subject><ispartof>2012 41st International Conference on Parallel Processing Workshops, 2012, p.135-139</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6337472$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6337472$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Bittner, R.</creatorcontrib><creatorcontrib>Ruf, E.</creatorcontrib><title>Direct GPU/FPGA Communication via PCI Express</title><title>2012 41st International Conference on Parallel Processing Workshops</title><addtitle>icppw</addtitle><description>Parallel processing has hit mainstream computing in the form of CPUs, GPUs and FPGAs. While explorations proceed with all three platforms individually and with the CPU-GPU pair, little exploration has been performed with the synergy of GPU-FPGA. This is due in part to the cumbersome nature of communication between the two. This paper presents a mechanism for direct GPU-FPGA communication and characterizes its performance in a full hardware implementation.</description><subject>Bandwidth</subject><subject>CUDA</subject><subject>Field programmable gate arrays</subject><subject>FPGA</subject><subject>GPU</subject><subject>Graphics processing unit</subject><subject>Hardware</subject><subject>Memory management</subject><subject>nVidia</subject><subject>Operating systems</subject><subject>PCI Express</subject><subject>PCIe</subject><subject>Switches</subject><subject>Verilog</subject><subject>Windows</subject><subject>Xilinx</subject><issn>0190-3918</issn><issn>2332-5690</issn><isbn>9781467325097</isbn><isbn>1467325090</isbn><isbn>9780769547954</isbn><isbn>0769547958</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjM1qwzAQhNU_qEl97KkXv4CSXUmWtMfgJq4hUB8ScgyKLINKnQTbLe3b17QdmPlgBoaxR4Q5ItCiKup6PxeAYoorlpKxYDTlyky-ZomQUvBcE9z8bqi0kSIHMrcsASTgktDes3QY3mCSFSgtJow_xz74MSvr3WJdl8usOHfdxyl6N8bzKfuMLquLKlt9XfowDA_srnXvQ0j_OWPb9WpbvPDNa1kVyw2PBCO3QRFI7y04fQTrtBO5VwKdap0SjQ7kbWiEDg2i8ngkl09927pWW1Jg5Yw9_d3GEMLh0sfO9d8HLaVRRsgfTC9Fmw</recordid><startdate>201209</startdate><enddate>201209</enddate><creator>Bittner, R.</creator><creator>Ruf, E.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201209</creationdate><title>Direct GPU/FPGA Communication via PCI Express</title><author>Bittner, R. ; Ruf, E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-8e4903cc80a6b08a6a25c421a4fa42d6e9c8ed26ed114c1b9a5a42ffaf6894083</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Bandwidth</topic><topic>CUDA</topic><topic>Field programmable gate arrays</topic><topic>FPGA</topic><topic>GPU</topic><topic>Graphics processing unit</topic><topic>Hardware</topic><topic>Memory management</topic><topic>nVidia</topic><topic>Operating systems</topic><topic>PCI Express</topic><topic>PCIe</topic><topic>Switches</topic><topic>Verilog</topic><topic>Windows</topic><topic>Xilinx</topic><toplevel>online_resources</toplevel><creatorcontrib>Bittner, R.</creatorcontrib><creatorcontrib>Ruf, E.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bittner, R.</au><au>Ruf, E.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Direct GPU/FPGA Communication via PCI Express</atitle><btitle>2012 41st International Conference on Parallel Processing Workshops</btitle><stitle>icppw</stitle><date>2012-09</date><risdate>2012</risdate><spage>135</spage><epage>139</epage><pages>135-139</pages><issn>0190-3918</issn><eissn>2332-5690</eissn><isbn>9781467325097</isbn><isbn>1467325090</isbn><eisbn>9780769547954</eisbn><eisbn>0769547958</eisbn><coden>IEEPAD</coden><abstract>Parallel processing has hit mainstream computing in the form of CPUs, GPUs and FPGAs. While explorations proceed with all three platforms individually and with the CPU-GPU pair, little exploration has been performed with the synergy of GPU-FPGA. This is due in part to the cumbersome nature of communication between the two. This paper presents a mechanism for direct GPU-FPGA communication and characterizes its performance in a full hardware implementation.</abstract><pub>IEEE</pub><doi>10.1109/ICPPW.2012.20</doi><tpages>5</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 0190-3918
ispartof 2012 41st International Conference on Parallel Processing Workshops, 2012, p.135-139
issn 0190-3918
2332-5690
language eng
recordid cdi_ieee_primary_6337472
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Bandwidth
CUDA
Field programmable gate arrays
FPGA
GPU
Graphics processing unit
Hardware
Memory management
nVidia
Operating systems
PCI Express
PCIe
Switches
Verilog
Windows
Xilinx
title Direct GPU/FPGA Communication via PCI Express
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-28T23%3A44%3A57IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Direct%20GPU/FPGA%20Communication%20via%20PCI%20Express&rft.btitle=2012%2041st%20International%20Conference%20on%20Parallel%20Processing%20Workshops&rft.au=Bittner,%20R.&rft.date=2012-09&rft.spage=135&rft.epage=139&rft.pages=135-139&rft.issn=0190-3918&rft.eissn=2332-5690&rft.isbn=9781467325097&rft.isbn_list=1467325090&rft.coden=IEEPAD&rft_id=info:doi/10.1109/ICPPW.2012.20&rft_dat=%3Cieee_6IE%3E6337472%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9780769547954&rft.eisbn_list=0769547958&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6337472&rfr_iscdi=true