SleepWalker: A 25-MHz 0.4-V Sub- \hbox^ 7- \mu\hbox Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes

Integrated circuits for wireless sensor nodes (WSNs) targeting the Internet-of-Things (IoT) paradigm require ultralow-power consumption for energy-harvesting operation and low die area for low-cost nodes. As the IoT calls for the deployment of trillions of WSNs, minimizing the carbon footprint for W...

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Veröffentlicht in:IEEE journal of solid-state circuits 2013-01, Vol.48 (1), p.20-32
Hauptverfasser: Bol, D., De Vos, J., Hocquet, C., Botman, F., Durvaux, F., Boyd, S., Flandre, D., Legat, J.
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container_end_page 32
container_issue 1
container_start_page 20
container_title IEEE journal of solid-state circuits
container_volume 48
creator Bol, D.
De Vos, J.
Hocquet, C.
Botman, F.
Durvaux, F.
Boyd, S.
Flandre, D.
Legat, J.
description Integrated circuits for wireless sensor nodes (WSNs) targeting the Internet-of-Things (IoT) paradigm require ultralow-power consumption for energy-harvesting operation and low die area for low-cost nodes. As the IoT calls for the deployment of trillions of WSNs, minimizing the carbon footprint for WSN chip manufacturing further emerges as a third target in a design-for-the-environment (DfE) perspective. The SleepWalker microcontroller is a 65-nm ultralow-voltage SoC based on the MSP430 architecture capable of delivering increased speed performances at 25 MHz for only 7 μW/MHz at 0.4 V. Its sub-mm 2 die area with low external component requirement ensures a low carbon footprint for chip manufacturing. SleepWalker incorporates an on-chip adaptive voltage scaling (AVS) system with DC/DC converter, clock generator, memories, sensor and communication interfaces, making it suited for WSN applications. An LP/GP process mix is fully exploited for minimizing the energy per cycle, with power gating to keep stand-by power at 1.7 μW. By incorporating a glitch-masking instruction cache, system power can be reduced by up to 52%. The AVS system ensures proper 25-MHz operation over process and temperature variations from -40 °C to +85 °C, with a peak efficiency of the DC/DC converter above 80%. Finally, a multi-V t clock tree reduces variability-induced clock skew by 3 × to ensure robust timing closure down to 0.3 V.
doi_str_mv 10.1109/JSSC.2012.2218067
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subjects Clocks
CMOS digital integrated circuits
DC-DC power converters
Delay
design for the environment (DfE)
Logic gates
near-threshold/subthreshold logic
System-on-a-chip
system-on-chip (SoC)
ultralow power
ultralow voltage
variability mitigation
Wireless sensor networks
title SleepWalker: A 25-MHz 0.4-V Sub- \hbox^ 7- \mu\hbox Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes
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