Performance of a Hardware Scheduler for Many-core Architecture
A hardware scheduler for many-core architectures enables fast scheduling and allocation of fine granularity tasks to all cores. We present performance evaluation of a hardware scheduler for HyperCore, a many-core architecture. The evaluation is based on an architectural simulator, using multiple ben...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 160 |
---|---|
container_issue | |
container_start_page | 151 |
container_title | |
container_volume | |
creator | Avron, I. Ginosar, R. |
description | A hardware scheduler for many-core architectures enables fast scheduling and allocation of fine granularity tasks to all cores. We present performance evaluation of a hardware scheduler for HyperCore, a many-core architecture. The evaluation is based on an architectural simulator, using multiple benchmarks representing a wide variety of inherent parallelism. Several architectural improvements are proposed, and various configurations of the scheduler are simulated. The results are analyzed, and are used to highlight the potential and the possible pitfalls of the architecture. It is shown that a scheduler with a capacity to schedule and terminate 10 instances per cycle, along with a task queue of as little as two slots near each core, is sufficient to utilize 256 cores. Other scheduling configurations are also analyzed. |
doi_str_mv | 10.1109/HPCC.2012.29 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6332171</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6332171</ieee_id><sourcerecordid>6332171</sourcerecordid><originalsourceid>FETCH-LOGICAL-i213t-121f57ec0a10d8c7c58dea7703e64bfd4bc6cfd6c04ff7daac3e0a2f5f3953c33</originalsourceid><addsrcrecordid>eNotj81Kw0AURkdE0Nbu3LmZF0i8d36TjVCCNkLFgrou0zt3aKRtZNIifXsDuvrgcDjwCXGHUCJC_dCumqZUgKpU9YWYgHe1Nd7U5lJM0DivFTpTXYvZMHwBAIK24P2NeFxxTn3ehwOx7JMMsg05_oTM8p22HE87znIU5Gs4nAvqRz7PtO2OTMdT5ltxlcJu4Nn_TsXn89NH0xbLt8VLM18WnUJ9LFBhsp4JAkKsyJOtIgfvQbMzmxTNhhyl6AhMSj6GQJohqGSTrq0mrafi_q_bMfP6O3f7kM9rp8dbHvUvSVhIsQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Performance of a Hardware Scheduler for Many-core Architecture</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Avron, I. ; Ginosar, R.</creator><creatorcontrib>Avron, I. ; Ginosar, R.</creatorcontrib><description>A hardware scheduler for many-core architectures enables fast scheduling and allocation of fine granularity tasks to all cores. We present performance evaluation of a hardware scheduler for HyperCore, a many-core architecture. The evaluation is based on an architectural simulator, using multiple benchmarks representing a wide variety of inherent parallelism. Several architectural improvements are proposed, and various configurations of the scheduler are simulated. The results are analyzed, and are used to highlight the potential and the possible pitfalls of the architecture. It is shown that a scheduler with a capacity to schedule and terminate 10 instances per cycle, along with a task queue of as little as two slots near each core, is sufficient to utilize 256 cores. Other scheduling configurations are also analyzed.</description><identifier>ISBN: 1467321648</identifier><identifier>ISBN: 9781467321648</identifier><identifier>EISBN: 0769547494</identifier><identifier>EISBN: 9780769547497</identifier><identifier>DOI: 10.1109/HPCC.2012.29</identifier><identifier>CODEN: IEEPAD</identifier><language>eng</language><publisher>IEEE</publisher><subject>Benchmark testing ; Hardware ; hardware scheduler ; many-core ; Multicore processing ; Processor scheduling ; Resource management ; Scheduling ; task queues</subject><ispartof>2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems, 2012, p.151-160</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6332171$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27904,54897</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6332171$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Avron, I.</creatorcontrib><creatorcontrib>Ginosar, R.</creatorcontrib><title>Performance of a Hardware Scheduler for Many-core Architecture</title><title>2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems</title><addtitle>hpcc-icess</addtitle><description>A hardware scheduler for many-core architectures enables fast scheduling and allocation of fine granularity tasks to all cores. We present performance evaluation of a hardware scheduler for HyperCore, a many-core architecture. The evaluation is based on an architectural simulator, using multiple benchmarks representing a wide variety of inherent parallelism. Several architectural improvements are proposed, and various configurations of the scheduler are simulated. The results are analyzed, and are used to highlight the potential and the possible pitfalls of the architecture. It is shown that a scheduler with a capacity to schedule and terminate 10 instances per cycle, along with a task queue of as little as two slots near each core, is sufficient to utilize 256 cores. Other scheduling configurations are also analyzed.</description><subject>Benchmark testing</subject><subject>Hardware</subject><subject>hardware scheduler</subject><subject>many-core</subject><subject>Multicore processing</subject><subject>Processor scheduling</subject><subject>Resource management</subject><subject>Scheduling</subject><subject>task queues</subject><isbn>1467321648</isbn><isbn>9781467321648</isbn><isbn>0769547494</isbn><isbn>9780769547497</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj81Kw0AURkdE0Nbu3LmZF0i8d36TjVCCNkLFgrou0zt3aKRtZNIifXsDuvrgcDjwCXGHUCJC_dCumqZUgKpU9YWYgHe1Nd7U5lJM0DivFTpTXYvZMHwBAIK24P2NeFxxTn3ehwOx7JMMsg05_oTM8p22HE87znIU5Gs4nAvqRz7PtO2OTMdT5ltxlcJu4Nn_TsXn89NH0xbLt8VLM18WnUJ9LFBhsp4JAkKsyJOtIgfvQbMzmxTNhhyl6AhMSj6GQJohqGSTrq0mrafi_q_bMfP6O3f7kM9rp8dbHvUvSVhIsQ</recordid><startdate>20120101</startdate><enddate>20120101</enddate><creator>Avron, I.</creator><creator>Ginosar, R.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>20120101</creationdate><title>Performance of a Hardware Scheduler for Many-core Architecture</title><author>Avron, I. ; Ginosar, R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i213t-121f57ec0a10d8c7c58dea7703e64bfd4bc6cfd6c04ff7daac3e0a2f5f3953c33</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Benchmark testing</topic><topic>Hardware</topic><topic>hardware scheduler</topic><topic>many-core</topic><topic>Multicore processing</topic><topic>Processor scheduling</topic><topic>Resource management</topic><topic>Scheduling</topic><topic>task queues</topic><toplevel>online_resources</toplevel><creatorcontrib>Avron, I.</creatorcontrib><creatorcontrib>Ginosar, R.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Avron, I.</au><au>Ginosar, R.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Performance of a Hardware Scheduler for Many-core Architecture</atitle><btitle>2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems</btitle><stitle>hpcc-icess</stitle><date>2012-01-01</date><risdate>2012</risdate><spage>151</spage><epage>160</epage><pages>151-160</pages><isbn>1467321648</isbn><isbn>9781467321648</isbn><eisbn>0769547494</eisbn><eisbn>9780769547497</eisbn><coden>IEEPAD</coden><abstract>A hardware scheduler for many-core architectures enables fast scheduling and allocation of fine granularity tasks to all cores. We present performance evaluation of a hardware scheduler for HyperCore, a many-core architecture. The evaluation is based on an architectural simulator, using multiple benchmarks representing a wide variety of inherent parallelism. Several architectural improvements are proposed, and various configurations of the scheduler are simulated. The results are analyzed, and are used to highlight the potential and the possible pitfalls of the architecture. It is shown that a scheduler with a capacity to schedule and terminate 10 instances per cycle, along with a task queue of as little as two slots near each core, is sufficient to utilize 256 cores. Other scheduling configurations are also analyzed.</abstract><pub>IEEE</pub><doi>10.1109/HPCC.2012.29</doi><tpages>10</tpages><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISBN: 1467321648 |
ispartof | 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems, 2012, p.151-160 |
issn | |
language | eng |
recordid | cdi_ieee_primary_6332171 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Benchmark testing Hardware hardware scheduler many-core Multicore processing Processor scheduling Resource management Scheduling task queues |
title | Performance of a Hardware Scheduler for Many-core Architecture |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T09%3A57%3A12IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Performance%20of%20a%20Hardware%20Scheduler%20for%20Many-core%20Architecture&rft.btitle=2012%20IEEE%2014th%20International%20Conference%20on%20High%20Performance%20Computing%20and%20Communication%20&%202012%20IEEE%209th%20International%20Conference%20on%20Embedded%20Software%20and%20Systems&rft.au=Avron,%20I.&rft.date=2012-01-01&rft.spage=151&rft.epage=160&rft.pages=151-160&rft.isbn=1467321648&rft.isbn_list=9781467321648&rft.coden=IEEPAD&rft_id=info:doi/10.1109/HPCC.2012.29&rft_dat=%3Cieee_6IE%3E6332171%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=0769547494&rft.eisbn_list=9780769547497&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6332171&rfr_iscdi=true |