A Full-Band processor for reduction of RF mixer LO harmonic images

A Full-Band processor for reduction of RF mixer LO harmonic images

A Full-Band Capture (FBC) Harmonic Rejection Canceler (HRC) processor is presented. This processor consists of an RF low-noise preamplifier, a 2700 Msamp/s 6-bit flash ADC, a digital channelizer which selects one or more interfering RF channels, and an adaptive canceler. This canceler removes the in...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Gomez, R., Zou, H., Chen, B., Currivan, B., Chang, D.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Harmonic analysis
Integrated circuits
Mixers
Noise
Power harmonic filters
Radio frequency
Receivers
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 4
container_issue
container_start_page 1
container_title
container_volume
creator Gomez, R.
Zou, H.
Chen, B.
Currivan, B.
Chang, D.
description A Full-Band Capture (FBC) Harmonic Rejection Canceler (HRC) processor is presented. This processor consists of an RF low-noise preamplifier, a 2700 Msamp/s 6-bit flash ADC, a digital channelizer which selects one or more interfering RF channels, and an adaptive canceler. This canceler removes the interference caused by strong blockers that may be inadvertently folded onto the desired channel by local oscillator (LO) harmonics or spurs. This processor digitizes the entire cable or broadcast television spectrum from 50-1000 MHz and can adaptively cancel folded blocker interference from anywhere within this range. An image reduction of at least 23dB was measured. The processor is embedded within an integrated 40nm CMOS DVB-T2 TV receiver including tuner, demodulator and FEC. The complete embedded RF/analog/DSP HRC processor has an area of 0.38 mm 2 and uses 205 mW.
doi_str_mv 10.1109/CICC.2012.6330614
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6330614</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6330614</ieee_id><sourcerecordid>6330614</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-5589d4c1e48da8a529cf203880241394d1ad0df1d30d3111fc8e983882797ce73</originalsourceid><addsrcrecordid>eNo1kMtqwzAURNUX1EnzAaUb_YDde_WwpWVi6jZgCJTsg5DkVsWPICXQ_n0NTRfDLA6cgSHkEaFABP1cb-u6YICsKDmHEsUVWaAoK45SCrgmGUPJcl5yuCErXal_JuUtyUCpMpeawz1ZpPQFgForlpHNmjbnvs83ZnT0GCfrU5oi7eZE7872FKaRTh19b-gQvn2k7Y5-mjhMY7A0DObDpwdy15k--dWll2TfvOzrt7zdvW7rdZsHDadcSqWdsOiFckYZybTtGHClgAnkWjg0DlyHjoPjiNhZ5bWaOat0ZX3Fl-TpTxu894djnMfjz-FyBf8Fo85L9g</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A Full-Band processor for reduction of RF mixer LO harmonic images</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Gomez, R. ; Zou, H. ; Chen, B. ; Currivan, B. ; Chang, D.</creator><creatorcontrib>Gomez, R. ; Zou, H. ; Chen, B. ; Currivan, B. ; Chang, D.</creatorcontrib><description>A Full-Band Capture (FBC) Harmonic Rejection Canceler (HRC) processor is presented. This processor consists of an RF low-noise preamplifier, a 2700 Msamp/s 6-bit flash ADC, a digital channelizer which selects one or more interfering RF channels, and an adaptive canceler. This canceler removes the interference caused by strong blockers that may be inadvertently folded onto the desired channel by local oscillator (LO) harmonics or spurs. This processor digitizes the entire cable or broadcast television spectrum from 50-1000 MHz and can adaptively cancel folded blocker interference from anywhere within this range. An image reduction of at least 23dB was measured. The processor is embedded within an integrated 40nm CMOS DVB-T2 TV receiver including tuner, demodulator and FEC. The complete embedded RF/analog/DSP HRC processor has an area of 0.38 mm 2 and uses 205 mW.</description><identifier>ISSN: 0886-5930</identifier><identifier>ISBN: 9781467315555</identifier><identifier>ISBN: 1467315559</identifier><identifier>EISSN: 2152-3630</identifier><identifier>EISBN: 1467315540</identifier><identifier>EISBN: 9781467315562</identifier><identifier>EISBN: 9781467315548</identifier><identifier>EISBN: 1467315567</identifier><identifier>DOI: 10.1109/CICC.2012.6330614</identifier><language>eng</language><publisher>IEEE</publisher><subject>Harmonic analysis ; Integrated circuits ; Mixers ; Noise ; Power harmonic filters ; Radio frequency ; Receivers</subject><ispartof>Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012, p.1-4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6330614$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,777,781,786,787,2052,27906,54901</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6330614$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Gomez, R.</creatorcontrib><creatorcontrib>Zou, H.</creatorcontrib><creatorcontrib>Chen, B.</creatorcontrib><creatorcontrib>Currivan, B.</creatorcontrib><creatorcontrib>Chang, D.</creatorcontrib><title>A Full-Band processor for reduction of RF mixer LO harmonic images</title><title>Proceedings of the IEEE 2012 Custom Integrated Circuits Conference</title><addtitle>CICC</addtitle><description>A Full-Band Capture (FBC) Harmonic Rejection Canceler (HRC) processor is presented. This processor consists of an RF low-noise preamplifier, a 2700 Msamp/s 6-bit flash ADC, a digital channelizer which selects one or more interfering RF channels, and an adaptive canceler. This canceler removes the interference caused by strong blockers that may be inadvertently folded onto the desired channel by local oscillator (LO) harmonics or spurs. This processor digitizes the entire cable or broadcast television spectrum from 50-1000 MHz and can adaptively cancel folded blocker interference from anywhere within this range. An image reduction of at least 23dB was measured. The processor is embedded within an integrated 40nm CMOS DVB-T2 TV receiver including tuner, demodulator and FEC. The complete embedded RF/analog/DSP HRC processor has an area of 0.38 mm 2 and uses 205 mW.</description><subject>Harmonic analysis</subject><subject>Integrated circuits</subject><subject>Mixers</subject><subject>Noise</subject><subject>Power harmonic filters</subject><subject>Radio frequency</subject><subject>Receivers</subject><issn>0886-5930</issn><issn>2152-3630</issn><isbn>9781467315555</isbn><isbn>1467315559</isbn><isbn>1467315540</isbn><isbn>9781467315562</isbn><isbn>9781467315548</isbn><isbn>1467315567</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kMtqwzAURNUX1EnzAaUb_YDde_WwpWVi6jZgCJTsg5DkVsWPICXQ_n0NTRfDLA6cgSHkEaFABP1cb-u6YICsKDmHEsUVWaAoK45SCrgmGUPJcl5yuCErXal_JuUtyUCpMpeawz1ZpPQFgForlpHNmjbnvs83ZnT0GCfrU5oi7eZE7872FKaRTh19b-gQvn2k7Y5-mjhMY7A0DObDpwdy15k--dWll2TfvOzrt7zdvW7rdZsHDadcSqWdsOiFckYZybTtGHClgAnkWjg0DlyHjoPjiNhZ5bWaOat0ZX3Fl-TpTxu894djnMfjz-FyBf8Fo85L9g</recordid><startdate>201209</startdate><enddate>201209</enddate><creator>Gomez, R.</creator><creator>Zou, H.</creator><creator>Chen, B.</creator><creator>Currivan, B.</creator><creator>Chang, D.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201209</creationdate><title>A Full-Band processor for reduction of RF mixer LO harmonic images</title><author>Gomez, R. ; Zou, H. ; Chen, B. ; Currivan, B. ; Chang, D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-5589d4c1e48da8a529cf203880241394d1ad0df1d30d3111fc8e983882797ce73</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Harmonic analysis</topic><topic>Integrated circuits</topic><topic>Mixers</topic><topic>Noise</topic><topic>Power harmonic filters</topic><topic>Radio frequency</topic><topic>Receivers</topic><toplevel>online_resources</toplevel><creatorcontrib>Gomez, R.</creatorcontrib><creatorcontrib>Zou, H.</creatorcontrib><creatorcontrib>Chen, B.</creatorcontrib><creatorcontrib>Currivan, B.</creatorcontrib><creatorcontrib>Chang, D.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gomez, R.</au><au>Zou, H.</au><au>Chen, B.</au><au>Currivan, B.</au><au>Chang, D.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Full-Band processor for reduction of RF mixer LO harmonic images</atitle><btitle>Proceedings of the IEEE 2012 Custom Integrated Circuits Conference</btitle><stitle>CICC</stitle><date>2012-09</date><risdate>2012</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><issn>0886-5930</issn><eissn>2152-3630</eissn><isbn>9781467315555</isbn><isbn>1467315559</isbn><eisbn>1467315540</eisbn><eisbn>9781467315562</eisbn><eisbn>9781467315548</eisbn><eisbn>1467315567</eisbn><abstract>A Full-Band Capture (FBC) Harmonic Rejection Canceler (HRC) processor is presented. This processor consists of an RF low-noise preamplifier, a 2700 Msamp/s 6-bit flash ADC, a digital channelizer which selects one or more interfering RF channels, and an adaptive canceler. This canceler removes the interference caused by strong blockers that may be inadvertently folded onto the desired channel by local oscillator (LO) harmonics or spurs. This processor digitizes the entire cable or broadcast television spectrum from 50-1000 MHz and can adaptively cancel folded blocker interference from anywhere within this range. An image reduction of at least 23dB was measured. The processor is embedded within an integrated 40nm CMOS DVB-T2 TV receiver including tuner, demodulator and FEC. The complete embedded RF/analog/DSP HRC processor has an area of 0.38 mm 2 and uses 205 mW.</abstract><pub>IEEE</pub><doi>10.1109/CICC.2012.6330614</doi><tpages>4</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 0886-5930
ispartof Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012, p.1-4
issn 0886-5930
2152-3630
language eng
recordid cdi_ieee_primary_6330614
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Harmonic analysis
Integrated circuits
Mixers
Noise
Power harmonic filters
Radio frequency
Receivers
title A Full-Band processor for reduction of RF mixer LO harmonic images
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-20T17%3A34%3A47IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20Full-Band%20processor%20for%20reduction%20of%20RF%20mixer%20LO%20harmonic%20images&rft.btitle=Proceedings%20of%20the%20IEEE%202012%20Custom%20Integrated%20Circuits%20Conference&rft.au=Gomez,%20R.&rft.date=2012-09&rft.spage=1&rft.epage=4&rft.pages=1-4&rft.issn=0886-5930&rft.eissn=2152-3630&rft.isbn=9781467315555&rft.isbn_list=1467315559&rft_id=info:doi/10.1109/CICC.2012.6330614&rft_dat=%3Cieee_6IE%3E6330614%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1467315540&rft.eisbn_list=9781467315562&rft.eisbn_list=9781467315548&rft.eisbn_list=1467315567&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6330614&rfr_iscdi=true