A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control
A 45nm CMOS 7b nonbinary 2b/cycle SAR ADC that operates up to 1GS/s with a 1.25V supply is presented. Use of a nonbinary decision scheme for decision error correction in a 2b/cycle structure not only increases the ADC speed with a relaxed DAC settling requirement but also makes the performance robus...
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| creator | Hyeok-Ki Hong Wan Kim Sun-Jae Park Choi, M. Ho-Jin Park Seung-Tak Ryu |
| description | A 45nm CMOS 7b nonbinary 2b/cycle SAR ADC that operates up to 1GS/s with a 1.25V supply is presented. Use of a nonbinary decision scheme for decision error correction in a 2b/cycle structure not only increases the ADC speed with a relaxed DAC settling requirement but also makes the performance robust to reference fluctuation and signal-dependent comparator offset variation. Proposed dynamic registers and a register-to-DAC direct control scheme enhance the conversion speed by minimizing logic delay in the decision loop. At a sampling rate of 1 GS/s, the chip achieves a peak SNDR of 41.6dB and maintains ENOB higher than 6b up to 1.3GHz signal frequency. The FoM is 80fJ/ conversion-step at 1GS/s with a power consumption of 7.2mW. |
| doi_str_mv | 10.1109/CICC.2012.6330609 |
| format | Conference Proceeding |
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The FoM is 80fJ/ conversion-step at 1GS/s with a power consumption of 7.2mW.</description><subject>2b/cycle SAR ADC</subject><subject>Capacitors</subject><subject>CMOS integrated circuits</subject><subject>Latches</subject><subject>nonbinary SAR ADC</subject><subject>Redundancy</subject><subject>Registers</subject><subject>Semiconductor device measurement</subject><subject>Switches</subject><issn>0886-5930</issn><issn>2152-3630</issn><isbn>9781467315555</isbn><isbn>1467315559</isbn><isbn>1467315540</isbn><isbn>9781467315562</isbn><isbn>9781467315548</isbn><isbn>1467315567</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo10MtKw0AYBeDxBqa1DyBu5gUm-Wf-zG0ZprUWCgVbcFkyyVRH0kSSgPTtrVhXZ3Hg8HEIeeSQcg42cyvnUgFcpAoRFNgrMuG50silzOGaJIJLwVAh3JCZ1ea_k_KWJGCMYtIi3JPJMHwCcGuNSMimoNpTvtxmA9WpOL7Rtmt9bMv-RIXPqlPVBLotXmkxd_Q7jh-0D-9xGEPPxo7NC0fr2IdqpFXXjn3XPJC7Q9kMYXbJKdk9L3buha03y5Ur1ixaGJnhIqBAXebK6DNYqVpoL3_RWHJlMNc2gNHWVLWXRvha-lyARl8fylxWOCVPf7MxhLD_6uPxDN5ffsEfRkxN1w</recordid><startdate>201209</startdate><enddate>201209</enddate><creator>Hyeok-Ki Hong</creator><creator>Wan Kim</creator><creator>Sun-Jae Park</creator><creator>Choi, M.</creator><creator>Ho-Jin Park</creator><creator>Seung-Tak Ryu</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201209</creationdate><title>A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control</title><author>Hyeok-Ki Hong ; Wan Kim ; Sun-Jae Park ; Choi, M. ; Ho-Jin Park ; Seung-Tak Ryu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-812e3237a468763066d27b597813a1683479e08798cdb582bd5b42073bdfa45c3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>2b/cycle SAR ADC</topic><topic>Capacitors</topic><topic>CMOS integrated circuits</topic><topic>Latches</topic><topic>nonbinary SAR ADC</topic><topic>Redundancy</topic><topic>Registers</topic><topic>Semiconductor device measurement</topic><topic>Switches</topic><toplevel>online_resources</toplevel><creatorcontrib>Hyeok-Ki Hong</creatorcontrib><creatorcontrib>Wan Kim</creatorcontrib><creatorcontrib>Sun-Jae Park</creatorcontrib><creatorcontrib>Choi, M.</creatorcontrib><creatorcontrib>Ho-Jin Park</creatorcontrib><creatorcontrib>Seung-Tak Ryu</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hyeok-Ki Hong</au><au>Wan Kim</au><au>Sun-Jae Park</au><au>Choi, M.</au><au>Ho-Jin Park</au><au>Seung-Tak Ryu</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control</atitle><btitle>Proceedings of the IEEE 2012 Custom Integrated Circuits Conference</btitle><stitle>CICC</stitle><date>2012-09</date><risdate>2012</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><issn>0886-5930</issn><eissn>2152-3630</eissn><isbn>9781467315555</isbn><isbn>1467315559</isbn><eisbn>1467315540</eisbn><eisbn>9781467315562</eisbn><eisbn>9781467315548</eisbn><eisbn>1467315567</eisbn><abstract>A 45nm CMOS 7b nonbinary 2b/cycle SAR ADC that operates up to 1GS/s with a 1.25V supply is presented. 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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0886-5930 |
| ispartof | Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012, p.1-4 |
| issn | 0886-5930 2152-3630 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | 2b/cycle SAR ADC Capacitors CMOS integrated circuits Latches nonbinary SAR ADC Redundancy Registers Semiconductor device measurement Switches |
| title | A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control |
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