A novel high speed & power efficient half adder design using MTCMOS Technique in 45 nanometre regime

A novel high speed low power half adder cell is proposed in this paper. The critical path consist of an AND gate and an EX-OR gate. This cell offers higher speed, lower power consumption than the standard implementation of the half adder. In this paper a MTCMOS (Multi Threshold Complementary Metal O...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Akashe, S., Tiwari, N. K., Shrivas, J., Sharma, R.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Adders CMOS CMOS integrated circuits CMOS technology Half Adder High Speed Logic gates Low Power MTCMOS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!