Design and implementation of a new symmetric Built-in Redundancy analyzer
With the advance of VLSI technology and growth of embedded memory density, a corresponding increase in the number of defects has resulted in yield and quality degradation. Built-in Self-Repair (BISR) solves this problem by replacing faulty cells with healthy redundant cells. Built-in Redundancy anal...
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| creator | Habiby, P. Asli, R. N. |
| description | With the advance of VLSI technology and growth of embedded memory density, a corresponding increase in the number of defects has resulted in yield and quality degradation. Built-in Self-Repair (BISR) solves this problem by replacing faulty cells with healthy redundant cells. Built-in Redundancy analyzer (BIRA) as a key component of BISR performs redundancy analysis and spare allocation. In this paper we used the symmetry feature of binary search tree to reduce the BIRA hardware overhead. Implementation results of the proposed BIRA for a 2×2 redundancy configuration are presented. |
| doi_str_mv | 10.1109/CADS.2012.6316427 |
| format | Conference Proceeding |
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Implementation results of the proposed BIRA for a 2×2 redundancy configuration are presented.</description><subject>Algorithm design and analysis</subject><subject>built-in redundancy analyzer</subject><subject>built-in self repair</subject><subject>Circuit faults</subject><subject>embedded memory</subject><subject>Maintenance engineering</subject><subject>Memory management</subject><subject>Redundancy</subject><subject>System-on-a-chip</subject><subject>Very large scale integration</subject><issn>2325-9361</issn><isbn>9781467314817</isbn><isbn>1467314811</isbn><isbn>146731482X</isbn><isbn>9781467314824</isbn><isbn>9781467314800</isbn><isbn>1467314803</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kEtLw0AUhUdUsNb8AHEzfyDx3pnJPJY19VEoCD7AXZkkNzKSTEuSIvHXW7ByFodvcb7FYewaIUMEd1sslq-ZABSZlqiVMCfsEpU2EpUVH6csccb-M5ozNhNS5KmTGi9YMgxfACDRWmv0jK2WNITPyH2seeh2LXUURz-GbeTbhnse6ZsPU9fR2IeK3-1DO6Yh8heq97H2sZoOS99OP9RfsfPGtwMlx56z94f7t-IpXT8_rorFOg1o8jFVQN4hSKup1iVUNvcOakGVco3yRroStVYm11BKPKRRdWkqaaWxIEAYOWc3f95ARJtdHzrfT5vjE_IX7WhOiw</recordid><startdate>201205</startdate><enddate>201205</enddate><creator>Habiby, P.</creator><creator>Asli, R. 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N.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Habiby, P.</au><au>Asli, R. N.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Design and implementation of a new symmetric Built-in Redundancy analyzer</atitle><btitle>The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012)</btitle><stitle>CADS</stitle><date>2012-05</date><risdate>2012</risdate><spage>99</spage><epage>103</epage><pages>99-103</pages><issn>2325-9361</issn><isbn>9781467314817</isbn><isbn>1467314811</isbn><eisbn>146731482X</eisbn><eisbn>9781467314824</eisbn><eisbn>9781467314800</eisbn><eisbn>1467314803</eisbn><abstract>With the advance of VLSI technology and growth of embedded memory density, a corresponding increase in the number of defects has resulted in yield and quality degradation. Built-in Self-Repair (BISR) solves this problem by replacing faulty cells with healthy redundant cells. Built-in Redundancy analyzer (BIRA) as a key component of BISR performs redundancy analysis and spare allocation. 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| issn | 2325-9361 |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis built-in redundancy analyzer built-in self repair Circuit faults embedded memory Maintenance engineering Memory management Redundancy System-on-a-chip Very large scale integration |
| title | Design and implementation of a new symmetric Built-in Redundancy analyzer |
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