Determination of worst case input combinations of nanoscale circuits using Bayesian networks

As MOSFETs are scaled down to nanometer dimensions, their performances and behaviours become less predictable. Designing reliable circuit or systems using these nano-transistors (nano-circuits or systems) post new challenges and require paradigm shift in design techniques, process and flow. In conve...

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Bibliographische Detailangaben

Hauptverfasser:	Khalid, U., Anwer, J., Singh, N., Hamid, N. H., Asirvadam, V. S.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Adders Bayesian methods Bayesian networks Integrated circuit modeling Integrated circuit reliability Nanoscale devices Probabilistic digital input Probabilistic logic Reliability Worst-case input combination
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