An FPGA implementation of shift converter block technique on FIFO for RS232 to universal serial bus converter
To meet the standard modern system communication demands, the paper represents the implementation of bidirectional shift converter technique for the embedded converter RS232 to Universal Serial Bus circuit block within FPGA using Verilog HDL language to be applied in a system wireless communication...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 224 |
|---|---|
| container_issue | |
| container_start_page | 219 |
| container_title | |
| container_volume | |
| creator | Jusoh, Nurul Fatihah Haron, M. A. Sulaiman, F. |
| description | To meet the standard modern system communication demands, the paper represents the implementation of bidirectional shift converter technique for the embedded converter RS232 to Universal Serial Bus circuit block within FPGA using Verilog HDL language to be applied in a system wireless communication within Zigbee protocol. Utilizing the ModelSim-Altera, RTL model of the shift converter was developed and synthesized then stimulated using TimeQuest Timing Analyzer to observe its functionality. |
| doi_str_mv | 10.1109/ICSGRC.2012.6287165 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6287165</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6287165</ieee_id><sourcerecordid>6287165</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-b1424390e1911365a583190a9a11686c252f4563bb015ee6db2a016a9c010d2a3</originalsourceid><addsrcrecordid>eNpFkM1qwzAQhFVKoW2aJ8hlX8CpVrIU62hMnRoCKUkOvQXZWRO1_kktpdC3ryGBzGUY-BiGYWyGfI7IzWuRbZebbC44irkWyQK1umPPGOuFFFzGn_e3oJJHNvX-i49aJIgon1ibdpB_LFNw7amhlrpgg-s76GvwR1cHqPrul4ZAA5RNX31DoOrYuZ8zwUjlRb6Guh9gsxVSQOjh3LkR97YBT4MbrTz7W8cLe6ht42l69Qnb5W-77D1arZdFlq4iZ3iISoxFLA0nNONGraxKJBpujUXUia6EEnWstCxLjopIH0phOWprKo78IKycsNml1hHR_jS41g5_--s78h_WWFgr</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>An FPGA implementation of shift converter block technique on FIFO for RS232 to universal serial bus converter</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Jusoh, Nurul Fatihah ; Haron, M. A. ; Sulaiman, F.</creator><creatorcontrib>Jusoh, Nurul Fatihah ; Haron, M. A. ; Sulaiman, F.</creatorcontrib><description>To meet the standard modern system communication demands, the paper represents the implementation of bidirectional shift converter technique for the embedded converter RS232 to Universal Serial Bus circuit block within FPGA using Verilog HDL language to be applied in a system wireless communication within Zigbee protocol. Utilizing the ModelSim-Altera, RTL model of the shift converter was developed and synthesized then stimulated using TimeQuest Timing Analyzer to observe its functionality.</description><identifier>ISBN: 1467320358</identifier><identifier>ISBN: 9781467320351</identifier><identifier>EISBN: 146732034X</identifier><identifier>EISBN: 9781467320368</identifier><identifier>EISBN: 9781467320344</identifier><identifier>EISBN: 1467320366</identifier><identifier>DOI: 10.1109/ICSGRC.2012.6287165</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; Engines ; Field programmable gate arrays ; FIFO ; FPGA ; Hardware design languages ; Protocols ; Registers ; Shift Converter ; UART ; Universal Serial Bus ; USB</subject><ispartof>2012 IEEE Control and System Graduate Research Colloquium, 2012, p.219-224</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6287165$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6287165$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jusoh, Nurul Fatihah</creatorcontrib><creatorcontrib>Haron, M. A.</creatorcontrib><creatorcontrib>Sulaiman, F.</creatorcontrib><title>An FPGA implementation of shift converter block technique on FIFO for RS232 to universal serial bus converter</title><title>2012 IEEE Control and System Graduate Research Colloquium</title><addtitle>ICSGRC</addtitle><description>To meet the standard modern system communication demands, the paper represents the implementation of bidirectional shift converter technique for the embedded converter RS232 to Universal Serial Bus circuit block within FPGA using Verilog HDL language to be applied in a system wireless communication within Zigbee protocol. Utilizing the ModelSim-Altera, RTL model of the shift converter was developed and synthesized then stimulated using TimeQuest Timing Analyzer to observe its functionality.</description><subject>Clocks</subject><subject>Engines</subject><subject>Field programmable gate arrays</subject><subject>FIFO</subject><subject>FPGA</subject><subject>Hardware design languages</subject><subject>Protocols</subject><subject>Registers</subject><subject>Shift Converter</subject><subject>UART</subject><subject>Universal Serial Bus</subject><subject>USB</subject><isbn>1467320358</isbn><isbn>9781467320351</isbn><isbn>146732034X</isbn><isbn>9781467320368</isbn><isbn>9781467320344</isbn><isbn>1467320366</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkM1qwzAQhFVKoW2aJ8hlX8CpVrIU62hMnRoCKUkOvQXZWRO1_kktpdC3ryGBzGUY-BiGYWyGfI7IzWuRbZebbC44irkWyQK1umPPGOuFFFzGn_e3oJJHNvX-i49aJIgon1ibdpB_LFNw7amhlrpgg-s76GvwR1cHqPrul4ZAA5RNX31DoOrYuZ8zwUjlRb6Guh9gsxVSQOjh3LkR97YBT4MbrTz7W8cLe6ht42l69Qnb5W-77D1arZdFlq4iZ3iISoxFLA0nNONGraxKJBpujUXUia6EEnWstCxLjopIH0phOWprKo78IKycsNml1hHR_jS41g5_--s78h_WWFgr</recordid><startdate>201207</startdate><enddate>201207</enddate><creator>Jusoh, Nurul Fatihah</creator><creator>Haron, M. A.</creator><creator>Sulaiman, F.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201207</creationdate><title>An FPGA implementation of shift converter block technique on FIFO for RS232 to universal serial bus converter</title><author>Jusoh, Nurul Fatihah ; Haron, M. A. ; Sulaiman, F.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-b1424390e1911365a583190a9a11686c252f4563bb015ee6db2a016a9c010d2a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Clocks</topic><topic>Engines</topic><topic>Field programmable gate arrays</topic><topic>FIFO</topic><topic>FPGA</topic><topic>Hardware design languages</topic><topic>Protocols</topic><topic>Registers</topic><topic>Shift Converter</topic><topic>UART</topic><topic>Universal Serial Bus</topic><topic>USB</topic><toplevel>online_resources</toplevel><creatorcontrib>Jusoh, Nurul Fatihah</creatorcontrib><creatorcontrib>Haron, M. A.</creatorcontrib><creatorcontrib>Sulaiman, F.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jusoh, Nurul Fatihah</au><au>Haron, M. A.</au><au>Sulaiman, F.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An FPGA implementation of shift converter block technique on FIFO for RS232 to universal serial bus converter</atitle><btitle>2012 IEEE Control and System Graduate Research Colloquium</btitle><stitle>ICSGRC</stitle><date>2012-07</date><risdate>2012</risdate><spage>219</spage><epage>224</epage><pages>219-224</pages><isbn>1467320358</isbn><isbn>9781467320351</isbn><eisbn>146732034X</eisbn><eisbn>9781467320368</eisbn><eisbn>9781467320344</eisbn><eisbn>1467320366</eisbn><abstract>To meet the standard modern system communication demands, the paper represents the implementation of bidirectional shift converter technique for the embedded converter RS232 to Universal Serial Bus circuit block within FPGA using Verilog HDL language to be applied in a system wireless communication within Zigbee protocol. Utilizing the ModelSim-Altera, RTL model of the shift converter was developed and synthesized then stimulated using TimeQuest Timing Analyzer to observe its functionality.</abstract><pub>IEEE</pub><doi>10.1109/ICSGRC.2012.6287165</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 1467320358 |
| ispartof | 2012 IEEE Control and System Graduate Research Colloquium, 2012, p.219-224 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_6287165 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks Engines Field programmable gate arrays FIFO FPGA Hardware design languages Protocols Registers Shift Converter UART Universal Serial Bus USB |
| title | An FPGA implementation of shift converter block technique on FIFO for RS232 to universal serial bus converter |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T13%3A34%3A20IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=An%20FPGA%20implementation%20of%20shift%20converter%20block%20technique%20on%20FIFO%20for%20RS232%20to%20universal%20serial%20bus%20converter&rft.btitle=2012%20IEEE%20Control%20and%20System%20Graduate%20Research%20Colloquium&rft.au=Jusoh,%20Nurul%20Fatihah&rft.date=2012-07&rft.spage=219&rft.epage=224&rft.pages=219-224&rft.isbn=1467320358&rft.isbn_list=9781467320351&rft_id=info:doi/10.1109/ICSGRC.2012.6287165&rft_dat=%3Cieee_6IE%3E6287165%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=146732034X&rft.eisbn_list=9781467320368&rft.eisbn_list=9781467320344&rft.eisbn_list=1467320366&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6287165&rfr_iscdi=true |