Generation and verification of tests for analogue circuits subject to process parameter deviations
The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking...
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| creator | Spinks, S.J. Chalk, C.D. Bell, I.M. Zwolinski, M. |
| description | The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analogue multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold, although they appear lower. |
| doi_str_mv | 10.1109/DFTVS.1997.628315 |
| format | Conference Proceeding |
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The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analogue multiplier circuit is presented. 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The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analogue multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold, although they appear lower.</description><subject>Analytical models</subject><subject>Circuit faults</subject><subject>Circuit simulation</subject><subject>Circuit testing</subject><subject>Current supplies</subject><subject>Electrical fault detection</subject><subject>Fault detection</subject><subject>Manufacturing processes</subject><subject>Predictive models</subject><subject>Sensitivity analysis</subject><issn>1550-5774</issn><issn>2377-7966</issn><isbn>0818681683</isbn><isbn>9780818681684</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1997</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkNtKAzEYhIMHsNY-gF7lBbbmTzaHvZRqq1DwwuptyW7-SEq7W5Jswbd36zo3A9_AwAwh98DmAKx6fF5uvj7mUFV6rrgRIC_IhAutC10pdUlumQGjDCgjrsgEpGSF1Lq8IbOUdmyQlAYqmJB6hS1Gm0PXUts6esIYfGhG0HmaMeVEfReH1O677x5pE2LTh4Gmvt5hk2nu6DF2DaZEjzbaA2aM1OEp_LWkO3Lt7T7h7N-n5HP5slm8Fuv31dviaV0E0DwXxtZumFKrEhxqJz0y5XjJATi3moFvRC24EA5AIpyRVLounSi1Z0ILMSUPY29AxO0xhoONP9vxHfELDdhYJg</recordid><startdate>1997</startdate><enddate>1997</enddate><creator>Spinks, S.J.</creator><creator>Chalk, C.D.</creator><creator>Bell, I.M.</creator><creator>Zwolinski, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1997</creationdate><title>Generation and verification of tests for analogue circuits subject to process parameter deviations</title><author>Spinks, S.J. ; Chalk, C.D. ; Bell, I.M. ; Zwolinski, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i172t-8abd628b641de7d5fe06d2421122a701fc3b3233d115e12a70567b4d347f03733</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1997</creationdate><topic>Analytical models</topic><topic>Circuit faults</topic><topic>Circuit simulation</topic><topic>Circuit testing</topic><topic>Current supplies</topic><topic>Electrical fault detection</topic><topic>Fault detection</topic><topic>Manufacturing processes</topic><topic>Predictive models</topic><topic>Sensitivity analysis</topic><toplevel>online_resources</toplevel><creatorcontrib>Spinks, S.J.</creatorcontrib><creatorcontrib>Chalk, C.D.</creatorcontrib><creatorcontrib>Bell, I.M.</creatorcontrib><creatorcontrib>Zwolinski, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Spinks, S.J.</au><au>Chalk, C.D.</au><au>Bell, I.M.</au><au>Zwolinski, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Generation and verification of tests for analogue circuits subject to process parameter deviations</atitle><btitle>1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems</btitle><stitle>DFTVS</stitle><date>1997</date><risdate>1997</risdate><spage>100</spage><epage>108</epage><pages>100-108</pages><issn>1550-5774</issn><eissn>2377-7966</eissn><isbn>0818681683</isbn><isbn>9780818681684</isbn><abstract>The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analogue multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold, although they appear lower.</abstract><pub>IEEE</pub><doi>10.1109/DFTVS.1997.628315</doi><tpages>9</tpages></addata></record> |
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| identifier | ISSN: 1550-5774 |
| ispartof | 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1997, p.100-108 |
| issn | 1550-5774 2377-7966 |
| language | eng |
| recordid | cdi_ieee_primary_628315 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analytical models Circuit faults Circuit simulation Circuit testing Current supplies Electrical fault detection Fault detection Manufacturing processes Predictive models Sensitivity analysis |
| title | Generation and verification of tests for analogue circuits subject to process parameter deviations |
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