A comparative study on asynchronous Quasi-Delay-Insensitive templates

The robustness of asynchronous logic has proved useful in dealing with contemporary problems in CMOS design such as process variations and power management. However, the general cryptic nature of asynchronous logic has stymied the widespread acceptance of this alternate design technique. Fortunately...

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Bibliographische Detailangaben

Hauptverfasser:	Chang, Kok-Leong, Lin, Tong, Ho, Weng-Geng, Chong, Kwen-Siong, Gwee, Bah-Hwee, Chang, Joseph S.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Detectors Pipelines Protocols System-on-a-chip Throughput Transistors Wires
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