DGECS: Description Generator for Evolved Circuits Synthesis

Evolvable Hardware (EHW) is an approach to the creation of hardware circuits based on a goal-oriented evolutionary process inspired by natural evolution. This approach allows the exploration of a very large design search space, ideally enabling to find solutions that are better in terms of resource...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Cancare, F., Bartolini, D. B., Carminati, M., Sciuto, D., Santambrogio, M. D.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 461
container_issue
container_start_page 454
container_title
container_volume
creator Cancare, F.
Bartolini, D. B.
Carminati, M.
Sciuto, D.
Santambrogio, M. D.
description Evolvable Hardware (EHW) is an approach to the creation of hardware circuits based on a goal-oriented evolutionary process inspired by natural evolution. This approach allows the exploration of a very large design search space, ideally enabling to find solutions that are better in terms of resource requirements, accuracy or timing performance, with respect to traditional design methods. To exploit this approach, it must be possible to port the evolved circuits to custom designs, however, in FPGA-based EHW systems (and, in particular, in the HERA project), the configuration bit stream for an evolved circuit is specific to the evolutionary platform and it cannot be ported to a different architecture. This paper expands the HERA framework with a tool able to export hardware circuits evolved within the HERA framework to an IP-core reusable in any PLB-based custom design. DGECS (Description Generator for Evolved Circuits Synthesis) permits to export evolved circuits to a VHDL description which can be then synthesized and plugged into a custom PLB architecture. Experimental results provide evidence that DGECS allows to correctly export evolved circuits, moreover, it enables to save resources thanks to the optimizations introduced by the synthesis flow it relies on.
doi_str_mv 10.1109/IPDPSW.2012.59
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6270678</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6270678</ieee_id><sourcerecordid>6270678</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-fe61d0eb44cea7b6f2ad0220af8463b110c3d6bcb31c4145f39644d2648662ca3</originalsourceid><addsrcrecordid>eNotjk1Lw0AURQdEqNZu3bjJH0icr7xJdCVJGguFFqK4LDOTNzhSkzITC_33BvTC5ezuuYTcM5oxRsvHzb7edx8Zp4xneXlFbpkEJWipZL4gqxi_6BxVMM7pDXmu26bqnpIaow3-NPlxSFocMOhpDImb25zH4xn7pPLB_vgpJt1lmD4x-nhHrp0-Rlz9c0ne181b9Zpud-2metmmnql8Sh0C6ykaKS1qZcBx3dNZrl0hQZj5sxU9GGsEs5LJ3IkSpOw5yAKAWy2W5OFv1yPi4RT8tw6XA3BFQRXiF5BgRPk</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>DGECS: Description Generator for Evolved Circuits Synthesis</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Cancare, F. ; Bartolini, D. B. ; Carminati, M. ; Sciuto, D. ; Santambrogio, M. D.</creator><creatorcontrib>Cancare, F. ; Bartolini, D. B. ; Carminati, M. ; Sciuto, D. ; Santambrogio, M. D.</creatorcontrib><description>Evolvable Hardware (EHW) is an approach to the creation of hardware circuits based on a goal-oriented evolutionary process inspired by natural evolution. This approach allows the exploration of a very large design search space, ideally enabling to find solutions that are better in terms of resource requirements, accuracy or timing performance, with respect to traditional design methods. To exploit this approach, it must be possible to port the evolved circuits to custom designs, however, in FPGA-based EHW systems (and, in particular, in the HERA project), the configuration bit stream for an evolved circuit is specific to the evolutionary platform and it cannot be ported to a different architecture. This paper expands the HERA framework with a tool able to export hardware circuits evolved within the HERA framework to an IP-core reusable in any PLB-based custom design. DGECS (Description Generator for Evolved Circuits Synthesis) permits to export evolved circuits to a VHDL description which can be then synthesized and plugged into a custom PLB architecture. Experimental results provide evidence that DGECS allows to correctly export evolved circuits, moreover, it enables to save resources thanks to the optimizations introduced by the synthesis flow it relies on.</description><identifier>ISBN: 1467309745</identifier><identifier>ISBN: 9781467309745</identifier><identifier>DOI: 10.1109/IPDPSW.2012.59</identifier><identifier>CODEN: IEEPAD</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit synthesis ; Field programmable gate arrays ; Hardware ; Routing ; Strontium ; Table lookup</subject><ispartof>2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &amp; PhD Forum, 2012, p.454-461</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6270678$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6270678$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Cancare, F.</creatorcontrib><creatorcontrib>Bartolini, D. B.</creatorcontrib><creatorcontrib>Carminati, M.</creatorcontrib><creatorcontrib>Sciuto, D.</creatorcontrib><creatorcontrib>Santambrogio, M. D.</creatorcontrib><title>DGECS: Description Generator for Evolved Circuits Synthesis</title><title>2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &amp; PhD Forum</title><addtitle>ipdpsw</addtitle><description>Evolvable Hardware (EHW) is an approach to the creation of hardware circuits based on a goal-oriented evolutionary process inspired by natural evolution. This approach allows the exploration of a very large design search space, ideally enabling to find solutions that are better in terms of resource requirements, accuracy or timing performance, with respect to traditional design methods. To exploit this approach, it must be possible to port the evolved circuits to custom designs, however, in FPGA-based EHW systems (and, in particular, in the HERA project), the configuration bit stream for an evolved circuit is specific to the evolutionary platform and it cannot be ported to a different architecture. This paper expands the HERA framework with a tool able to export hardware circuits evolved within the HERA framework to an IP-core reusable in any PLB-based custom design. DGECS (Description Generator for Evolved Circuits Synthesis) permits to export evolved circuits to a VHDL description which can be then synthesized and plugged into a custom PLB architecture. Experimental results provide evidence that DGECS allows to correctly export evolved circuits, moreover, it enables to save resources thanks to the optimizations introduced by the synthesis flow it relies on.</description><subject>Circuit synthesis</subject><subject>Field programmable gate arrays</subject><subject>Hardware</subject><subject>Routing</subject><subject>Strontium</subject><subject>Table lookup</subject><isbn>1467309745</isbn><isbn>9781467309745</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjk1Lw0AURQdEqNZu3bjJH0icr7xJdCVJGguFFqK4LDOTNzhSkzITC_33BvTC5ezuuYTcM5oxRsvHzb7edx8Zp4xneXlFbpkEJWipZL4gqxi_6BxVMM7pDXmu26bqnpIaow3-NPlxSFocMOhpDImb25zH4xn7pPLB_vgpJt1lmD4x-nhHrp0-Rlz9c0ne181b9Zpud-2metmmnql8Sh0C6ykaKS1qZcBx3dNZrl0hQZj5sxU9GGsEs5LJ3IkSpOw5yAKAWy2W5OFv1yPi4RT8tw6XA3BFQRXiF5BgRPk</recordid><startdate>201205</startdate><enddate>201205</enddate><creator>Cancare, F.</creator><creator>Bartolini, D. B.</creator><creator>Carminati, M.</creator><creator>Sciuto, D.</creator><creator>Santambrogio, M. D.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201205</creationdate><title>DGECS: Description Generator for Evolved Circuits Synthesis</title><author>Cancare, F. ; Bartolini, D. B. ; Carminati, M. ; Sciuto, D. ; Santambrogio, M. D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-fe61d0eb44cea7b6f2ad0220af8463b110c3d6bcb31c4145f39644d2648662ca3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Circuit synthesis</topic><topic>Field programmable gate arrays</topic><topic>Hardware</topic><topic>Routing</topic><topic>Strontium</topic><topic>Table lookup</topic><toplevel>online_resources</toplevel><creatorcontrib>Cancare, F.</creatorcontrib><creatorcontrib>Bartolini, D. B.</creatorcontrib><creatorcontrib>Carminati, M.</creatorcontrib><creatorcontrib>Sciuto, D.</creatorcontrib><creatorcontrib>Santambrogio, M. D.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Cancare, F.</au><au>Bartolini, D. B.</au><au>Carminati, M.</au><au>Sciuto, D.</au><au>Santambrogio, M. D.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>DGECS: Description Generator for Evolved Circuits Synthesis</atitle><btitle>2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &amp; PhD Forum</btitle><stitle>ipdpsw</stitle><date>2012-05</date><risdate>2012</risdate><spage>454</spage><epage>461</epage><pages>454-461</pages><isbn>1467309745</isbn><isbn>9781467309745</isbn><coden>IEEPAD</coden><abstract>Evolvable Hardware (EHW) is an approach to the creation of hardware circuits based on a goal-oriented evolutionary process inspired by natural evolution. This approach allows the exploration of a very large design search space, ideally enabling to find solutions that are better in terms of resource requirements, accuracy or timing performance, with respect to traditional design methods. To exploit this approach, it must be possible to port the evolved circuits to custom designs, however, in FPGA-based EHW systems (and, in particular, in the HERA project), the configuration bit stream for an evolved circuit is specific to the evolutionary platform and it cannot be ported to a different architecture. This paper expands the HERA framework with a tool able to export hardware circuits evolved within the HERA framework to an IP-core reusable in any PLB-based custom design. DGECS (Description Generator for Evolved Circuits Synthesis) permits to export evolved circuits to a VHDL description which can be then synthesized and plugged into a custom PLB architecture. Experimental results provide evidence that DGECS allows to correctly export evolved circuits, moreover, it enables to save resources thanks to the optimizations introduced by the synthesis flow it relies on.</abstract><pub>IEEE</pub><doi>10.1109/IPDPSW.2012.59</doi><tpages>8</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 1467309745
ispartof 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012, p.454-461
issn
language eng
recordid cdi_ieee_primary_6270678
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Circuit synthesis
Field programmable gate arrays
Hardware
Routing
Strontium
Table lookup
title DGECS: Description Generator for Evolved Circuits Synthesis
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T13%3A47%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=DGECS:%20Description%20Generator%20for%20Evolved%20Circuits%20Synthesis&rft.btitle=2012%20IEEE%2026th%20International%20Parallel%20and%20Distributed%20Processing%20Symposium%20Workshops%20&%20PhD%20Forum&rft.au=Cancare,%20F.&rft.date=2012-05&rft.spage=454&rft.epage=461&rft.pages=454-461&rft.isbn=1467309745&rft.isbn_list=9781467309745&rft.coden=IEEPAD&rft_id=info:doi/10.1109/IPDPSW.2012.59&rft_dat=%3Cieee_6IE%3E6270678%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6270678&rfr_iscdi=true