Epitaxialy defined (ED) FinFET: to reduce VT variability and enable multiple VT

Device variability has become a major concern for CMOS technology [1]. Various sources of variability include Random Dopant Fluctuation (RDF), Gate Edge Roughness (GER) and Line Edge Roughness (LER) [2]. The introduction of FinFETs at 22nm node has two issues. Firstly, the effect of RDF is considerably reduced due to undoped fins [3]. But the aggressive fin width (Wfin) requirement (~Lg/3 [4]) to reduce short channel effect aggravates the electrical impact of LER and makes it greatest contributor to patterning induced variability [2]. Moreover, the edge roughness does not scale with technology and remains independent of the type of lithography used [5]. Secondly, multiple threshold voltage (V T ) is achieved in planar technology by various patterned implant steps, which is unavailable for FinFET technology as the fin is undoped. Multiple V T transistor technology is essential for power vs. performance optimization by circuit designers [6]. In this work, we propose an alternative to conventional FinFET structure which can (a) reduce overall variability by 4× reduction in sensitivity to LER and (b) enable multiple V T by applying body bias dynamically without any costly patterned implant steps.