Low power CMOS full adder cells
This paper presents low power CMOS full adder cells. The full adder cells are utilization to low power by using XOR and XNOR gate architectures with pass transistor logic and transmission gate. All simulation results have been carried out by using HSPICE program simulator based on 22 nm CMOS technol...
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| creator | Sudsakorn, A. Tooprakai, S. Dejhan, K. |
| description | This paper presents low power CMOS full adder cells. The full adder cells are utilization to low power by using XOR and XNOR gate architectures with pass transistor logic and transmission gate. All simulation results have been carried out by using HSPICE program simulator based on 22 nm CMOS technology at 1.2 V supply voltages. The operating frequency is 250 MHz. In comparison with other 1 bit adder cells, simulation results show that have used low power consumption and power delay product of SUM and C OUT . |
| doi_str_mv | 10.1109/ECTICon.2012.6254174 |
| format | Conference Proceeding |
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The full adder cells are utilization to low power by using XOR and XNOR gate architectures with pass transistor logic and transmission gate. All simulation results have been carried out by using HSPICE program simulator based on 22 nm CMOS technology at 1.2 V supply voltages. The operating frequency is 250 MHz. In comparison with other 1 bit adder cells, simulation results show that have used low power consumption and power delay product of SUM and C OUT .</description><identifier>ISBN: 1467320269</identifier><identifier>ISBN: 9781467320269</identifier><identifier>EISBN: 1467320250</identifier><identifier>EISBN: 1467320242</identifier><identifier>EISBN: 9781467320252</identifier><identifier>EISBN: 9781467320245</identifier><identifier>DOI: 10.1109/ECTICon.2012.6254174</identifier><language>eng</language><publisher>IEEE</publisher><subject>Adders ; CMOS full adder ; CMOS integrated circuits ; CMOS technology ; Logic gates ; low power full adder ; XNOR-XOR gate</subject><ispartof>2012 9th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, 2012, p.1-4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6254174$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,27904,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6254174$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Sudsakorn, A.</creatorcontrib><creatorcontrib>Tooprakai, S.</creatorcontrib><creatorcontrib>Dejhan, K.</creatorcontrib><title>Low power CMOS full adder cells</title><title>2012 9th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology</title><addtitle>ECTICon</addtitle><description>This paper presents low power CMOS full adder cells. The full adder cells are utilization to low power by using XOR and XNOR gate architectures with pass transistor logic and transmission gate. All simulation results have been carried out by using HSPICE program simulator based on 22 nm CMOS technology at 1.2 V supply voltages. The operating frequency is 250 MHz. In comparison with other 1 bit adder cells, simulation results show that have used low power consumption and power delay product of SUM and C OUT .</description><subject>Adders</subject><subject>CMOS full adder</subject><subject>CMOS integrated circuits</subject><subject>CMOS technology</subject><subject>Logic gates</subject><subject>low power full adder</subject><subject>XNOR-XOR gate</subject><isbn>1467320269</isbn><isbn>9781467320269</isbn><isbn>1467320250</isbn><isbn>1467320242</isbn><isbn>9781467320252</isbn><isbn>9781467320245</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFj81KxDAUhSMiqOM8gYJ9gdZ7kzY3XUoYdaAyC7sf8nMDlWiHVhl8ewsOeDaHb_NxjhB3CBUitA8b22_t-FlJQFlp2dRI9Zm4xlqTkiAbOP8H3V6K9Ty_wxIyiEpdiftuPBaH8chTYV93b0X6zrlwMS4cOOf5Rlwkl2den3ol-qdNb1_Kbve8tY9dObTwVbYeo_PgWDXKACHUWofIEQxITAmZoglkZPAaCEimQMqz1rgM8QBRrcTtn3Zg5v1hGj7c9LM__VG_wb88_Q</recordid><startdate>201205</startdate><enddate>201205</enddate><creator>Sudsakorn, A.</creator><creator>Tooprakai, S.</creator><creator>Dejhan, K.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201205</creationdate><title>Low power CMOS full adder cells</title><author>Sudsakorn, A. ; Tooprakai, S. ; Dejhan, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-9b1dab0ae35380710466cded08021ff1e7d8c782cb607072fc73be661007b00d3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Adders</topic><topic>CMOS full adder</topic><topic>CMOS integrated circuits</topic><topic>CMOS technology</topic><topic>Logic gates</topic><topic>low power full adder</topic><topic>XNOR-XOR gate</topic><toplevel>online_resources</toplevel><creatorcontrib>Sudsakorn, A.</creatorcontrib><creatorcontrib>Tooprakai, S.</creatorcontrib><creatorcontrib>Dejhan, K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sudsakorn, A.</au><au>Tooprakai, S.</au><au>Dejhan, K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Low power CMOS full adder cells</atitle><btitle>2012 9th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology</btitle><stitle>ECTICon</stitle><date>2012-05</date><risdate>2012</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><isbn>1467320269</isbn><isbn>9781467320269</isbn><eisbn>1467320250</eisbn><eisbn>1467320242</eisbn><eisbn>9781467320252</eisbn><eisbn>9781467320245</eisbn><abstract>This paper presents low power CMOS full adder cells. The full adder cells are utilization to low power by using XOR and XNOR gate architectures with pass transistor logic and transmission gate. All simulation results have been carried out by using HSPICE program simulator based on 22 nm CMOS technology at 1.2 V supply voltages. The operating frequency is 250 MHz. In comparison with other 1 bit adder cells, simulation results show that have used low power consumption and power delay product of SUM and C OUT .</abstract><pub>IEEE</pub><doi>10.1109/ECTICon.2012.6254174</doi><tpages>4</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Adders CMOS full adder CMOS integrated circuits CMOS technology Logic gates low power full adder XNOR-XOR gate |
| title | Low power CMOS full adder cells |
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